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公开(公告)号:US20240088039A1
公开(公告)日:2024-03-14
申请号:US18512527
申请日:2023-11-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jungho DO , Sanghoon BAEK
IPC: H01L23/528 , H01L27/02 , H01L27/092 , H01L29/423 , H01L29/786
CPC classification number: H01L23/5286 , H01L27/0207 , H01L27/092 , H01L29/42392 , H01L29/78696
Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.
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公开(公告)号:US20220246601A1
公开(公告)日:2022-08-04
申请号:US17720153
申请日:2022-04-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sanghoon BAEK , Myung Gil KANG , Jae-Ho PARK , Seung Young LEE
IPC: H01L27/02 , H01L27/092 , H01L29/786 , H01L29/06 , H01L29/423 , H01L27/118
Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.
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公开(公告)号:US20210074697A1
公开(公告)日:2021-03-11
申请号:US16842053
申请日:2020-04-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sanghoon BAEK , Myung Gil KANG , Jae-Ho PARK , Seung Young LEE
IPC: H01L27/02 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786
Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.
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公开(公告)号:US20220208757A1
公开(公告)日:2022-06-30
申请号:US17562428
申请日:2021-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jungho DO , Sanghoon BAEK
IPC: H01L27/06 , H01L23/528
Abstract: An integrated circuit device is provided. The integrated circuit device includes: a substrate with a first active area and a second active area spaced apart from each other in a first horizontal direction; a plurality of normal cells arranged on a first surface of the substrate; a power wiring structure arranged on a second surface of the substrate; and a power gating cell arranged on the first surface of the substrate. The power gating cell includes: a sleep control transistor arranged in the first active area; and a through via penetrating the second active area of the substrate. The power gating cell is configured to provide a virtual power voltage to the plurality of normal cells through a virtual power line based on a power voltage supplied from the power wiring structure through the through via and a power line.
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公开(公告)号:US20220059460A1
公开(公告)日:2022-02-24
申请号:US17323407
申请日:2021-05-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jungho DO , Sanghoon BAEK
IPC: H01L23/528 , H01L27/092 , H01L27/02 , H01L29/423 , H01L29/786
Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.
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公开(公告)号:US20220122970A1
公开(公告)日:2022-04-21
申请号:US17323707
申请日:2021-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jungho DO , Sanghoon BAEK
IPC: H01L27/088 , H01L29/66 , H01L27/06 , H01L23/50 , H01L23/522 , H01L29/78
Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.
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公开(公告)号:US20220114320A1
公开(公告)日:2022-04-14
申请号:US17458948
申请日:2021-08-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jisu YU , Jaewoo SEO , Hyeongyu YOU , Sanghoon BAEK , Jonghoon JUNG
IPC: G06F30/392 , H01L27/02 , H01L23/50
Abstract: An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.
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公开(公告)号:US20210313310A1
公开(公告)日:2021-10-07
申请号:US17158109
申请日:2021-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ji Su YU , Jae-Woo SEO , Sanghoon BAEK , Hyeon Gyu YOU
IPC: H01L27/02 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , G06F30/392
Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.
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公开(公告)号:US20180350838A1
公开(公告)日:2018-12-06
申请号:US16043236
申请日:2018-07-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Taejoong SONG , Ha-Young KIM , Jung-Ho DO , Sanghoon BAEK , Jinyoung LIM , Kwangok JEONG
IPC: H01L27/118 , H01L21/66 , G06F17/50 , H01L49/02 , H01L27/11582 , H01L27/092 , H01L27/02 , G03F1/36 , H01L21/8238
CPC classification number: H01L27/11807 , G03F1/36 , G06F17/5045 , G06F17/505 , G06F17/5077 , G06F17/5081 , H01L21/823821 , H01L21/823878 , H01L22/20 , H01L27/0207 , H01L27/0924 , H01L27/11582 , H01L28/00 , H01L2027/11831 , H01L2027/11881
Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.
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公开(公告)号:US20170062475A1
公开(公告)日:2017-03-02
申请号:US15282206
申请日:2016-09-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Taejoong SONG , Ha-Young KIM , Jung-Ho DO , Sanghoon BAEK , Jinyoung LIM , Kwangok JEONG
IPC: H01L27/118 , G03F1/36 , G06F17/50
CPC classification number: H01L27/11807 , G03F1/36 , G06F17/5045 , G06F17/505 , G06F17/5077 , G06F17/5081 , H01L21/823821 , H01L21/823878 , H01L22/20 , H01L27/0207 , H01L27/0924 , H01L27/11582 , H01L28/00 , H01L2027/11831 , H01L2027/11881
Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.
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