公开(公告)号：US20230120496A1

公开(公告)日：2023-04-20

申请号：US18046656

申请日：2022-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keunhwi Cho ,  Gibum Kim ,  Myunggil Kang ,  Dongwon Kim

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, an active fin on the substrate, and a transistor on the active fin. The transistor includes a lower channel layer, an intermediate channel layer, and an upper channel layer sequentially stacked, and a gate structure traversing the active fin, respectively surrounding the channel layers, and including a gate dielectric and a gate electrode. The gate electrode includes a lower electrode portion between the active fin and the lower channel layer, an intermediate electrode portion between the lower channel layer and the intermediate channel layer, and an upper electrode portion between the intermediate channel layer and the upper channel layer. The gate electrode includes a work function adjusting metal element, and a content of the work function adjusting metal element in the lower electrode portion is different from that in each of the intermediate electrode portion and the upper electrode portion.

公开(公告)号：US11574905B2

公开(公告)日：2023-02-07

申请号：US17371494

申请日：2021-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woocheol Shin ,  Myunggil Kang ,  Minyi Kim ,  Sanghoon Lee

IPC: H01L21/00 ,  H01L27/06 ,  H01L21/8234

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

公开(公告)号：US20200381555A1

公开(公告)日：2020-12-03

申请号：US16815744

申请日：2020-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Lee ,  Krishna Bhuwalka ,  Myunggil Kang ,  Kyoungmin Choi

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).

公开(公告)号：US12249606B2

公开(公告)日：2025-03-11

申请号：US18414039

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Keunhwi Cho ,  Myunggil Kang ,  Seokhoon Kim ,  Dongwon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20240072149A1

公开(公告)日：2024-02-29

申请号：US18195749

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggwon KIM ,  Myunggil Kang ,  Dongwon Kim ,  Beomjin Park ,  Inu Jeon ,  Soojin Jeong

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode layer crossing the active region and extending in a second direction, a plurality of channel layers on the active region, spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and disposed sequentially from the active region, and surrounded by the gate electrode layer, gate spacer layers disposed on side surfaces of the gate electrode layer in the first direction, and source/drain regions disposed on the active region, on sides of the gate electrode layer, and connected to the plurality of channel layers. An uppermost channel layer among the plurality of channel layers includes channel portions separated from each other in the first direction and disposed below the gate spacer layers.

公开(公告)号：US11901363B2

公开(公告)日：2024-02-13

申请号：US17382149

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Myunggil Kang ,  Kang-Ill Seo

IPC: H01L27/12 ,  H01L23/535 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/822 ,  H01L27/06 ,  H01L27/092 ,  G01R27/02

CPC classification number: H01L27/1203 ,  G01R27/02 ,  H01L23/535 ,  H01L27/1211

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US11888039B2

公开(公告)日：2024-01-30

申请号：US17352973

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghee Park ,  Myunggil Kang ,  Uihui Kwon ,  Seungkyu Kim ,  Ahyoung Kim ,  Youngseok Song

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/41775 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region.

公开(公告)号：US11631674B2

公开(公告)日：2023-04-18

申请号：US17231114

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Choi ,  Keunhwi Cho ,  Myunggil Kang ,  Seokhoon Kim ,  Dongwon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US11282928B2

公开(公告)日：2022-03-22

申请号：US15931964

申请日：2020-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keunhwi Cho ,  Byounghak Hong ,  Myunggil Kang

IPC: H01L29/161 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor device including an active structure on a substrate, the active structure including silicon germanium patterns and silicon patterns alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on sidewalls of the active structure that face in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source/drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction that is perpendicular to the first direction, wherein the silicon germanium patterns are silicon rich-silicon germanium.

公开(公告)号：US11075197B2

公开(公告)日：2021-07-27

申请号：US16784788

申请日：2020-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woocheol Shin ,  Myunggil Kang ,  Minyi Kim ,  Sanghoon Lee

IPC: H01L21/00 ,  H01L27/06 ,  H01L21/8234

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.