公开(公告)号：US20240071438A1

公开(公告)日：2024-02-29

申请号：US18051142

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar PULLURU ,  Gopi Sunanth Kumar Gogineni ,  Manish Chandra Joshi ,  Pushp Khatter

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/109 ,  G11C7/12 ,  G11C7/22

Abstract: Various example embodiments of the inventive concepts include a SRAM apparatus including a left memory array and right memory array, each of the left memory array and the right memory array including a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, and each of the segments comprising a plurality of memory bit cells, and central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments.

公开(公告)号：US20210118494A1

公开(公告)日：2021-04-22

申请号：US16720888

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ambuj JAIN ,  Akash Kumar Gupta ,  Manish Chandra Joshi ,  Parvinder Kumar Rana ,  Abhishek Kesarwani

IPC: G11C11/419

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

公开(公告)号：US10147493B2

公开(公告)日：2018-12-04

申请号：US15665988

申请日：2017-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Parvinder Kumar Rana ,  Lava Kumar Pulluru ,  Manish Chandra Joshi

IPC: G11C16/32 ,  G11C16/08

Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.