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11.发明授权公开(公告)号：US12185543B2
公开(公告)日：2024-12-31
申请号：US17742043
申请日：2022-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sanghun Chun , Kwangyoung Jung , Youngji Noh , Junghwan Park , Jeehoon Han
Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.
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公开(公告)号：US20240422975A1
公开(公告)日：2024-12-19
申请号：US18590354
申请日：2024-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwangyoung Jung , Sunil Shim , Seung-Jun Lee , Joohyun Lim , Yoojin Jeon
Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure on a peripheral substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a cell array region and an outer region, a source structure on the cell array region, a base pattern on the outer region, a cell vertical structure that extends into the cell array structure in the cell array region and is electrically connected to the source structure, an outer vertical structure that extends into the cell array structure in the outer region, and a filling pattern that extends from the outer vertical structure and into the base pattern. The filling pattern defines a void, a top end of the cell vertical structure extends from the peripheral substrate by a first distance, and a top surface of the source structure extends from the peripheral substrate by a second distance.
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公开(公告)号：US20230360881A1
公开(公告)日：2023-11-09
申请号：US18139639
申请日：2023-04-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Youngmin Min , Jungan Kwon , Gillhoon Shin , Keechun Shim , Daeseong Ha , Kyoungsuk Kim , Seungmin Ryu , Hyunsuk Park , Jiho Uh , Hyunjoon Ohn , Hyeseon Lee
IPC: H01J37/32
CPC classification number: H01J37/32082 , H01J2237/334 , H01J2237/24585 , H01J2237/24564
Abstract: A radio frequency (RF) generator including a carbonization prevention system includes a casing on which an intake fan and an interlock are mounted, an alternating current (AC) power supply, a power supply, a power amplifier (PA), a coupler provided between the PA and the RF output connector, and a control board that controls an amount of DC power output to the PA according to the calculated values. The carbonization prevention system detects smoke generated in the casing, measures a temperature and a humidity in the casing, and generates and transmits a control signal to the control board and an operation control signal to the interlock according to a reading result.
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公开(公告)号：US20230262972A1
公开(公告)日：2023-08-17
申请号：US18190253
申请日：2023-03-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangyoun JO , Kohji Kanamori , Kwangyoung Jung , Jeehoon Han
IPC: H10B41/27 , H01L23/528 , H01L23/522 , H10B41/10 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/40
CPC classification number: H10B41/27 , H01L23/528 , H01L23/5226 , H10B41/10 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/40
Abstract: A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.
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公开(公告)号：US10741574B2
公开(公告)日：2020-08-11
申请号：US15955256
申请日：2018-04-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwangyoung Jung , Jongwon Kim , Dongseog Eun , Joonhee Lee
IPC: H01L27/11568 , H01L27/11582 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11565 , H01L27/11575
Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.
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Patent Agency Ranking
公开(公告)号：US12279421B2
公开(公告)日：2025-04-15
申请号：US18190253
申请日：2023-03-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangyoun Jo , Kohji Kanamori , Kwangyoung Jung , Jeehoon Han
IPC: H10B41/27 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/40
Abstract: A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.
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公开(公告)号：US12022658B2
公开(公告)日：2024-06-25
申请号：US18356064
申请日：2023-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Sangyoun Jo , Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/40 , G11C7/18 , G11C16/08 , H10B41/10 , H10B41/27 , H10B41/43 , H10B43/10 , H10B43/27
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
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公开(公告)号：US20230371260A1
公开(公告)日：2023-11-16
申请号：US18356064
申请日：2023-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Sangyoun Jo , Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/40 , G11C7/18 , G11C16/08 , H10B41/10 , H10B41/27 , H10B41/43 , H10B43/10 , H10B43/27
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
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公开(公告)号：US11778834B2
公开(公告)日：2023-10-03
申请号：US17983024
申请日：2022-11-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangyoung Jung , Sangyoun Jo , Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/40 , G11C7/18 , G11C16/08 , H10B41/10 , H10B41/27 , H10B41/43 , H10B43/10 , H10B43/27
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
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公开(公告)号：US20200335520A1
公开(公告)日：2020-10-22
申请号：US16921185
申请日：2020-07-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwangyoung Jung , Jongwon Kim , Dongseog Eun , Joonhee Lee
IPC: H01L27/11582 , H01L27/11568 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11565 , H01L27/11575
Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.
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