公开(公告)号：US20250126846A1

公开(公告)日：2025-04-17

申请号：US18613829

申请日：2024-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung KWON ,  Changhyun KIM ,  Kyung-Eun BYUN ,  Minsu SEOL

IPC: H01L29/786 ,  H01L29/41 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a first channel layer and a second channel layer spaced from each other in a first direction and each include a two-dimensional (2D) semiconductor material, a first source electrode between the first channel layer and the second channel layer to be simultaneously in contact with the first channel layer and the second channel layer, a first drain electrode between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and simultaneously in contact with the first channel layer and the second channel layer, a first gate electrode arranged in a first internal space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer, and a first gate insulating layer surrounding the first gate electrode in the first internal space.

公开(公告)号：US20250107096A1

公开(公告)日：2025-03-27

申请号：US18581186

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonchoo CHO ,  Junyoung KWON ,  Huije RYU ,  Minsu SEOL

IPC: H10B43/30 ,  H10B43/27

Abstract: A memory device may include a gate electrode, a channel layer spaced apart from the gate electrode, a charge trap layer between the gate electrode and the channel layer, and a two-dimensional material layer arranged between the charge trap layer and the gate electrode. The two-dimensional material layer may include a material having an electron affinity of less than 1 eV.

公开(公告)号：US20240021679A1

公开(公告)日：2024-01-18

申请号：US18350433

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Junyoung KWON ,  Keunwook SHIN ,  Minseok YOO

IPC: H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/775

CPC classification number: H01L29/24 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/7853 ,  H01L29/775 ,  H01L29/04

Abstract: A semiconductor device may include a two-dimensional material layer including a two-dimensional semiconductor material having a polycrystalline structure; metallic nanoparticles partially on the two-dimensional material layer; a source electrode and a drain electrode respectively on both sides of the two-dimensional material layer; and a gate insulating layer and a gate electrode on the two-dimensional material layer between the source electrode and the drain electrode.

公开(公告)号：US20230036321A1

公开(公告)日：2023-02-02

申请号：US17831950

申请日：2022-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Junyoung KWON ,  Minseok YOO

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8238

Abstract: Provided are a layer structure including a configuration capable of increasing the operation characteristics of a device including the layer structure, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure includes a first layer and a second layer on one surface of the first layer and facing the first layer. The first layer and the second layer overlap each other. One layer of the first layer and the second layer has a trace of applied strain, and an other layer of the first layer and the second layer is a strain-inducing layer that applies a strain to the one layer.

公开(公告)号：US20240186183A1

公开(公告)日：2024-06-06

申请号：US18441520

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Minhyun LEE ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/0259 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66045 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/78696

Abstract: Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

公开(公告)号：US20240038845A1

公开(公告)日：2024-02-01

申请号：US18335487

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minseok YOO ,  Minsu SEOL ,  Junyoung KWON ,  Kyung-Eun BYUN

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/1033 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/66795 ,  H01L29/66431 ,  H01L29/41791

Abstract: A layer structure including a two-dimensional (2D) channel layer, a method of manufacturing a two-dimensional (2D) channel layer, an electronic device including the layer structure, and an electronic apparatus including the layer structure are disclosed. The layer structure may include a first substrate, a second substrate surrounded by the first substrate, and a 2D channel layer on the second substrate. An interfacial energy of the second substrate may be less than an interfacial energy of the first substrate. The method of manufacturing a 2D channel layer may include forming a second substrate to be surrounded by a first substrate, forming a precursor layer for forming a 2D channel on any one of the first and second substrates, and transforming the precursor layer into a liquid precursor layer. The interfacial energy of the second substrate may be less than the interfacial energy of the first substrate.

公开(公告)号：US20240014303A1

公开(公告)日：2024-01-11

申请号：US18153633

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung KWON ,  Minsu Seol ,  Keunwook Shin ,  Minseok Yoo

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7606 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/78642 ,  H01L29/78696 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/66969

Abstract: A semiconductor device includes a substrate including a gate electrode therein, a trench penetrating the gate electrode and arranged in the substrate, a gate insulating layer in the trench and an upper surface of the substrate, a channel layer on the gate insulating layer and including a two-dimensional (2D) semiconductor material, and a source electrode and a drain electrode, which are spaced apart from each other on the channel layer.

公开(公告)号：US20220238721A1

公开(公告)日：2022-07-28

申请号：US17505955

申请日：2021-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Minsu SEOL ,  Eunkyu LEE ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO

IPC: H01L29/786

Abstract: A semiconductor device according to an embodiment may include a substrate, an adhesive layer, and a semiconductor layer. The semiconductor layer includes a 2D material having a layered structure. The adhesive layer is interposed between the substrate and the semiconductor layer, and has adhesiveness to a 2D material.

公开(公告)号：US20220238692A1

公开(公告)日：2022-07-28

申请号：US17546303

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Minsu SEOL ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO ,  Yeonchoo CHO

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/304 ,  H01L21/463

Abstract: A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region.

公开(公告)号：US20250142894A1

公开(公告)日：2025-05-01

申请号：US18752024

申请日：2024-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Huije RYU ,  Junyoung KWON ,  Changhyun KIM ,  Minsu SEOL

IPC: H01L29/786 ,  H01L21/3115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device may include a two-dimensional (2D) material layer extending in a first direction, a source electrode and a drain electrode each electrically connected to the 2D material layer, an insulating layer arranged on the 2D material layer, and a gate electrode arranged apart from the 2D material layer in a second direction perpendicular to the first direction, wherein the insulating layer includes a dopant.