公开(公告)号：US20210043648A1

公开(公告)日：2021-02-11

申请号：US16850097

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Seonho YOON ,  Bonghyun CHOI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

公开(公告)号：US20210005620A1

公开(公告)日：2021-01-07

申请号：US16835559

申请日：2020-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Jisung CHEON

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11548

Abstract: A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.

公开(公告)号：US20240064981A1

公开(公告)日：2024-02-22

申请号：US18386112

申请日：2023-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Seonho YOON ,  Bonghyun CHOI

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

公开(公告)号：US20230247829A1

公开(公告)日：2023-08-03

申请号：US18132019

申请日：2023-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Jisung CHEON

IPC: H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.

公开(公告)号：US20230232632A1

公开(公告)日：2023-07-20

申请号：US18188946

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Geunwon Lim ,  Manjoong Kim

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US20230217661A1

公开(公告)日：2023-07-06

申请号：US17961070

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbum WOO ,  Joonsung LIM ,  Junhyoung KIM ,  Seungmin LEE

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device includes a contact plug forming a signal path electrically connecting a bitline or wordlines and an upper connection pattern to each other, a lower insulating structure includes first and second insulating portions; the contact plug penetrates through the second insulating portion and contacts the upper connection pattern; the first insulating portion includes first and second lower layers, the second lower layer having a thickness smaller than the first lower layer; the second insulating portion includes a first upper layer contacting the second lower layer and covering a portion of an upper surface of the upper connection pattern, and a second upper layer on the first upper layer, the second upper layer having a thickness greater than the first upper layer; and materials of the second lower layer and first upper layer is different from materials of the first lower layer and the second upper layer.

公开(公告)号：US20220399360A1

公开(公告)日：2022-12-15

申请号：US17721533

申请日：2022-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoon SON ,  Junhyoung KIM

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524

Abstract: A semiconductor device and a data storage system including the same are provided. The semiconductor device including a plate layer, a pattern structure on the plate layer, an upper pattern layer on the pattern structure, an upper structure including a stack structure and a capping insulating structure covering at least a portion of the stack structure, the stack structure including interlayer insulating layers and gate layers alternately stacked on each other, and separation structures and vertical memory structures penetrating through the upper structure, the upper pattern layer, and the pattern structure, and extending into the plate layer may be provided.

公开(公告)号：US20210399010A1

公开(公告)日：2021-12-23

申请号：US17204010

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Youngjin KWON ,  Jeongeun KIM ,  Byunggon PARK ,  Sungwon CHO

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11595 ,  H01L23/528

Abstract: A memory device includes a lower structure, a stacked structure on the lower structure, the stacked structure including horizontal layers and interlayer insulating layers alternately stacked in a vertical direction, and each of the horizontal layers including a gate electrode, a vertical structure penetrating through the stacked structure in the vertical direction, the vertical structure having a core region, a pad pattern with a pad metal pattern on the core region, a dielectric structure including a first portion facing a side surface of the core region, a second portion facing at least a portion of a side surface of the pad metal pattern, and a data storage layer, and a channel layer between the dielectric structure and the core region, a contact structure on the vertical structure, and a conductive line on the contact structure.

公开(公告)号：US20250056806A1

公开(公告)日：2025-02-13

申请号：US18610514

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Bumkyu KANG ,  Junyong PARK ,  Sukkang SUNG

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device and a data storage system are provided. The semiconductor device includes a peripheral circuit structure; a stack structure vertically overlapping the peripheral circuit structure; and a separation structure penetrating through the stack structure. The stack structure includes a plurality of blocks spaced apart from each other by a first portion of the separation structure, each of the plurality of blocks includes insulating layers and conductive layers alternately stacked in a vertical direction, and the plurality of blocks include first blocks and a plurality of capacitor blocks disposed between first blocks adjacent to each other among the first blocks.

公开(公告)号：US20230403866A1

公开(公告)日：2023-12-14

申请号：US18297266

申请日：2023-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Myunghun Lee

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L21/768

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L21/76898 ,  H10B41/27

Abstract: A semiconductor device may include a first substrate structure including a plate layer, gate electrodes stacked on the plate layer, channel structures penetrating through the gate electrodes, and first bonding metal layers on the channel structures; and a second substrate structure connected to the first substrate structure, and including a substrate having active regions, device isolation layers in the substrate defining the active regions, circuit devices on one surface of the substrate, and second bonding metal layers connected to the first bonding metal layers, the device isolation layers including first device isolation layers and a second device isolation layer having different heights, and the active regions including first active regions spaced apart by the first device isolation layers and connected to each other by the substrate, and second active regions separated from the first active regions by the second device isolation layer.