公开(公告)号：US20190279920A1

公开(公告)日：2019-09-12

申请号：US16426612

申请日：2019-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Jung-Hoon Han ,  Dong-Sik Park

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/538

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

公开(公告)号：US10056339B2

公开(公告)日：2018-08-21

申请号：US15628349

申请日：2017-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeon-Woo Jang ,  Junghwan Park ,  Ramakanth Kappaganthu ,  Sungjin Kim ,  Junyong Noh ,  Jung-Hoon Han ,  Seung Soo Kim ,  Sungjin Kim ,  Sojung Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L2924/3512

Abstract: A semiconductor device includes a substrate, a first insulation layer, data storage elements, a contact plug, and a first dummy dam. The first insulation layer is on the substrate and includes a pad region and a peripheral region adjacent to the pad region. The data storage elements are on the pad region of the first insulation layer. The contact plug penetrates the first insulation layer on the peripheral region. The first dummy dam penetrates the first insulation layer and is disposed between the data storage elements and the contact plug.

公开(公告)号：US20170098630A1

公开(公告)日：2017-04-06

申请号：US15246586

申请日：2016-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Park ,  Jung-Hoon Han

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor chip is provided including an integrated circuit on a substrate; pads electrically connected to the integrated circuit; a lower insulating structure defining contact holes exposing the pads, respectively; and first, second and third conductive patterns electrically connected to the pads. The second conductive pattern is between the first conductive pattern and the third conductive pattern when viewed from a plan view. Each of the first to third conductive patterns includes a contact portion filling the contact hole, a first conductive line portion extending in one direction on the lower insulating structure, and a bonding pad portion. Ends of the bonding pad portions of the first and third conductive patterns protrude in the one direction as compared with an end of the bonding pad portion of the second conductive pattern when viewed from a plan view.

公开(公告)号：US20150221557A1

公开(公告)日：2015-08-06

申请号：US14452665

申请日：2014-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheon-Bae Kim ,  Jung-Hoon Han ,  Byung-Hoon Cho

IPC: H01L21/8234 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/823475 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a wiring structure, a carbon-containing layer may be formed on a substrate. A conductive layer may be formed on the carbon-containing layer, and the conductive layer may be formed to include a metal. The conductive layer and an upper portion of the carbon-containing layer may be etched to form a wiring and a carbon-containing layer pattern, respectively.

Abstract translation: 在形成布线结构的方法中，可以在基板上形成含碳层。 可以在含碳层上形成导电层，并且可以形成导电层以包括金属。 可以蚀刻导电层和含碳层的上部以形成布线和含碳层图案。

公开(公告)号：US12218212B2

公开(公告)日：2025-02-04

申请号：US18496336

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doosan Back ,  Dongoh Kim ,  Gyuhyun Kil ,  Jung-Hoon Han

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/51

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

公开(公告)号：US11545554B2

公开(公告)日：2023-01-03

申请号：US17406162

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doosan Back ,  Dongoh Kim ,  Gyuhyun Kil ,  Jung-Hoon Han

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/51

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

公开(公告)号：US11139199B2

公开(公告)日：2021-10-05

申请号：US16420328

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Seokhwan Kim ,  Joodong Kim ,  Junyong Noh ,  Jaewon Seo

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

公开(公告)号：US20210305190A1

公开(公告)日：2021-09-30

申请号：US17146550

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin Choi ,  Jung-Hoon Han ,  Yeonjin Lee ,  Jong-Min Lee ,  Jihoon Chang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66

Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

公开(公告)号：US11075181B2

公开(公告)日：2021-07-27

申请号：US16418036

申请日：2019-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Dong-Wan Kim ,  Dongho Kim ,  Jaewon Seo

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/67

Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

公开(公告)号：US10790186B2

公开(公告)日：2020-09-29

申请号：US15984524

申请日：2018-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Chan-Sic Yoon ,  Ilyoung Moon ,  Jemin Park ,  Kiseok Lee ,  Jung-Hoon Han

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.