知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.019 seconds)

    Memory device and operation method thereof
    11.
    发明授权
    Memory device and operation method thereof 有权

    公开(公告)号：US12119063B2

    公开(公告)日：2024-10-15

    申请号：US17957532

    申请日：2022-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Wan Nam ,  Hyunggon Kim ,  Bong-Kil Jung ,  Younho Hong ,  Juseong Hwang

    IPC: G11C16/08

    CPC classification number: G11C16/08

    Abstract: Disclosed is a memory device includes a memory block that is connected with a plurality of wordlines, a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines, and an address decoding circuit configured to connect the plurality of driving lines with unselected wordlines of the plurality of wordlines. During a wordline setup period for the plurality of wordlines, the voltage generating circuit floats first driving lines corresponding to first unselected wordlines of the unselected wordlines from among the plurality of driving lines when the first unselected wordlines reach a first target level, and floats second driving lines corresponding to second unselected wordlines of the unselected wordlines from among the plurality of driving lines when the second unselected wordlines reach a second target level different from the first target level.

    Method of counting number of cells in nonvolatile memory device and nonvolatile memory device with cell counter performing the same
    13.
    发明授权
    Method of counting number of cells in nonvolatile memory device and nonvolatile memory device with cell counter performing the same 有权

    公开(公告)号：US11636892B2

    公开(公告)日：2023-04-25

    申请号：US17346171

    申请日：2021-06-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minseok Kim ,  Hyunggon Kim

    IPC: G11C16/08 ,  G11C11/4091 ,  G11C11/4074 ,  G11C16/34 ,  G11C16/04 ,  G11C11/4076 ,  G11C11/4099 ,  G11C16/26

    Abstract: In a method of counting the number of memory cells in a nonvolatile memory device, a measurement range and a plurality of measurement intervals of a measurement window for a cell counting operation are set to a first range and a plurality of first intervals, respectively. The plurality of measurement intervals are included in the measurement range. A first sensing operation is performed on first memory cells included in a first region of a memory cell array based on the measurement window. A first shifting operation for shifting the measurement window is performed while a width of the measurement range and a width of each of the plurality of measurement intervals are maintained. A second sensing operation is performed on the first memory cells based on the measurement window shifted by the first shifting operation. A final count value for the first memory cells is obtained based on a result of the first sensing operation and a result of the second sensing operation.

    Negative level shifters and nonvolatile memory devices including the same
    15.
    发明授权
    Negative level shifters and nonvolatile memory devices including the same 有权

    公开(公告)号：US11443810B2

    公开(公告)日：2022-09-13

    申请号：US17220368

    申请日：2021-04-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sooyeol Yang ,  Hyunggon Kim ,  Youngsun Song

    IPC: G11C16/12 ,  H01L27/11582 ,  H01L27/11573

    Abstract: A negative level shifter includes a shifting circuit and a latch circuit. The shifting circuit shifts levels of a first input signal and a second input signal to provide a first output signal and a second output signal having complementary levels at a first output node and a second output node, respectively, using low voltage transistors and high voltage transistors having different characteristics. The latch circuit, connected to the shifting circuit at the first output node and the second output node, latches the first output signal and the second output signal, receives a negative voltage having a level smaller than a ground voltage, and drives the second output signal and the first output signal complementarily to either a level of a power supply voltage or a level of the negative voltage, based on voltage levels at the first output node and the second output node, respectively.

    Page buffer including latches and memory device including the page buffer
    17.
    发明授权
    Page buffer including latches and memory device including the page buffer 有权

    公开(公告)号：US11848069B2

    公开(公告)日：2023-12-19

    申请号：US17718070

    申请日：2022-04-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Keeho Jung ,  Sangwan Nam ,  Hyunggon Kim

    IPC: G11C7/00 ,  G11C7/10 ,  G11C7/06 ,  G11C7/12

    CPC classification number: G11C7/1039 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

    Abstract: The memory device includes a page buffer circuit including a page buffer connected to each of a plurality of bit lines. The page buffer includes at least one additional latch and N number of data latches, and a control logic circuit that controls a setting of the page buffer. Based on a first setting, data programmed in a current program operation is stored in some of the N data latches and the at least one additional latch, and data which is to be programmed in a next program operation before the current program operation is completed is stored in some other of the N data latches and the at least one additional latches. Based on a second setting, externally provided data is not stored in the at least one additional latch in the current program operation and the next program operation.

    METHOD OF COUNTING NUMBER OF CELLS IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE SAME
    20.
    发明申请
    METHOD OF COUNTING NUMBER OF CELLS IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE SAME 有权

    公开(公告)号：US20220093160A1

    公开(公告)日：2022-03-24

    申请号：US17346171

    申请日：2021-06-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minseok Kim ,  Hyunggon Kim

    IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4099 ,  G11C11/4076

    Abstract: In a method of counting the number of memory cells in a nonvolatile memory device, a measurement range and a plurality of measurement intervals of a measurement window for a cell counting operation are set to a first range and a plurality of first intervals, respectively. The plurality of measurement intervals are included in the measurement range. A first sensing operation is performed on first memory cells included in a first region of a memory cell array based on the measurement window. A first shifting operation for shifting the measurement window is performed while a width of the measurement range and a width of each of the plurality of measurement intervals are maintained. A second sensing operation is performed on the first memory cells based on the measurement window shifted by the first shifting operation. A final count value for the first memory cells is obtained based on a result of the first sensing operation and a result of the second sensing operation.

Patent Agency Ranking