公开(公告)号：US20240145023A1

公开(公告)日：2024-05-02

申请号：US18341192

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Wook SEO ,  SangYong Yoon ,  Keeho Jung

IPC: G11C29/46 ,  G11C29/12

CPC classification number: G11C29/46 ,  G11C29/1201

Abstract: A memory device includes a test mode detector circuit that determines whether the memory device has entered a test mode based on at least one test mode entry signal received through at least one pin of a plurality of pins and generates a test mode detection signal, and a test pad connection circuit that electrically couples a first pin of the plurality of pins to a dedicated test pad of the test mode such that a signal applied to the first pin is transmitted to the dedicated test pad based on the test mode detection signal.

公开(公告)号：US12100463B2

公开(公告)日：2024-09-24

申请号：US17954663

申请日：2022-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongkil Jung ,  Sangwan Nam ,  Keeho Jung

IPC: G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C29/20 ,  G11C16/04

CPC classification number: G11C29/12015 ,  G11C29/025 ,  G11C29/14 ,  G11C29/20 ,  G11C16/0483

Abstract: Provided are a memory device detecting a defect and an operating method thereof. The memory device includes a memory cell area including a memory cell array that stores data, and a peripheral circuit area including a control logic configured to control operations of the memory cell array, wherein the peripheral circuit area further includes a defect detection circuit, the defect detection circuit being configured to generate a count result value by selecting a first input signal from a plurality of input signals and counting at least one time interval of the first input signal based on a clock signal, and to detect a defect of the first input signal by comparing an expected value with the count result value, and the at least one time interval is a length of time in which logic low or logic high is maintained.

公开(公告)号：US20240231697A1

公开(公告)日：2024-07-11

申请号：US18469931

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keeho Jung ,  Suchang Jeon

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory device includes a memory cell array having a plurality of cell blocks therein, including at least one cell block configured to store information data read (IDR) data related to setting an operating environment of the memory device. A setting data storage circuit is provided, which includes a plurality of storage regions in which the IDR data, which is read from the at least one cell block, is stored and a reset operation is independently controlled. Control logic is provided, which is configured to control at least one of a reset operation on the setting data storage circuit, and an IDR operation of updating the IDR data to the setting data storage circuit according to a decoding result of an external command. The control logic is configured to selectively reset only some storage regions of the setting data storage circuit in response to a determination that the external command is a first reset command, but reset all storage regions of the setting data storage circuit in response to a determination that the external command is a second reset command.

公开(公告)号：US11848069B2

公开(公告)日：2023-12-19

申请号：US17718070

申请日：2022-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keeho Jung ,  Sangwan Nam ,  Hyunggon Kim

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1039 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

Abstract: The memory device includes a page buffer circuit including a page buffer connected to each of a plurality of bit lines. The page buffer includes at least one additional latch and N number of data latches, and a control logic circuit that controls a setting of the page buffer. Based on a first setting, data programmed in a current program operation is stored in some of the N data latches and the at least one additional latch, and data which is to be programmed in a next program operation before the current program operation is completed is stored in some other of the N data latches and the at least one additional latches. Based on a second setting, externally provided data is not stored in the at least one additional latch in the current program operation and the next program operation.