公开(公告)号：US10749042B2

公开(公告)日：2020-08-18

申请号：US16400443

申请日：2019-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk Kim ,  Dae Hyun Jang ,  Seung Pil Chung ,  Sung II Cho

IPC: H01L29/792 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.

公开(公告)号：US20230262960A1

公开(公告)日：2023-08-17

申请号：US18160692

申请日：2023-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yejeong Seo ,  Hyuk Kim

IPC: H10B12/00 ,  H01L23/48

CPC classification number: H10B12/315 ,  H01L23/481 ,  H10B12/482

Abstract: A semiconductor device includes a substrate, a data storage structure on the substrate, an insulating structure spaced apart from the data storage structure on the substrate, conductive lines spaced apart from each other and stacked in a vertical direction between the data storage structure and the insulating structure, active layers spaced apart from each other and stacked in the vertical direction between the data storage structure and the insulating structure, and intersecting the conductive lines, and a conductive pattern between the insulating structure and the active layers, and electrically connected to the active layers. The insulating structure includes first insulating patterns spaced apart from each other in a first horizontal direction, and a second insulating pattern between the first insulating patterns. The conductive pattern is between the second insulating pattern and the active layers. The second insulating pattern includes a material different from that of the first insulating patterns.

公开(公告)号：US20190066983A1

公开(公告)日：2019-02-28

申请号：US15945001

申请日：2018-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Edward Sung ,  Hyuk Kim ,  Daehyun Jang ,  Sung II Cho

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/683

Abstract: Shrouds and substrate treating systems including the same are provided. Substrate treating systems may include a process chamber, a supporter, and a plasma source that is spaced apart from the supporter in a vertical direction. The substrate treating systems may also include a shroud configured to contain the plasma therein. The shroud may include a sidewall portion and a first flange portion extending horizontally from the sidewall portion and including a plurality of first slits that extend through a thickness of the first flange portion. The first flange portion may define a first opening, and a portion of the supporter may extend through the first opening. The sidewall portion may include a plurality of second slits, and each of the plurality of second slits may extend through a thickness of the sidewall portion and may extend from one of the plurality of first slits toward the plasma source.

公开(公告)号：US09865540B2

公开(公告)日：2018-01-09

申请号：US15207610

申请日：2016-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk Kim ,  Jae-Ho Min ,  Jong-Kyoung Park ,  Seung-Pil Chung

IPC: H01L29/792 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/1157

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines.