公开(公告)号：US20190214423A1

公开(公告)日：2019-07-11

申请号：US16058451

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-uk Han

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0557 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/16104 ,  H01L2224/16145

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US20240321857A1

公开(公告)日：2024-09-26

申请号：US18736766

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L24/97 ,  H01L24/08 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08146 ,  H01L2224/80001 ,  H01L2225/06541

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

公开(公告)号：US20240055406A1

公开(公告)日：2024-02-15

申请号：US18364802

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongseon Kim ,  Dohyun Kim ,  Juhyeon Kim ,  Hyoeun Kim ,  Seonkyung Seo ,  Chajea Jo

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/105 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05541 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/08121 ,  H01L2224/08148 ,  H01L2224/08235 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/38

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.

公开(公告)号：US20230013176A1

公开(公告)日：2023-01-19

申请号：US17656011

申请日：2022-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/78

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

公开(公告)号：US11990452B2

公开(公告)日：2024-05-21

申请号：US18120587

申请日：2023-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namhoon Kim ,  Chajea Jo ,  Ohguk Kwon ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L25/0652 ,  H01L2224/02372 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

公开(公告)号：US20240128236A1

公开(公告)日：2024-04-18

申请号：US18359031

申请日：2023-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoeun Kim ,  Dohyun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L22/32 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/09055 ,  H01L2224/09515 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/37001

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.

公开(公告)号：US11887913B2

公开(公告)日：2024-01-30

申请号：US18066487

申请日：2022-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Ohguk Kwon ,  Namhoon Kim ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/562 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0652 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/13026 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/351

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US11869818B2

公开(公告)日：2024-01-09

申请号：US17733411

申请日：2022-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Yonghoe Cho ,  Sunkyoung Seo ,  Seunghoon Yeon ,  Sanguk Han

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  G01R31/28 ,  G01R27/26

CPC classification number: H01L22/32 ,  G01R27/2605 ,  G01R31/2818 ,  H01L22/14 ,  H01L23/3128 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513

Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

公开(公告)号：US20230118535A1

公开(公告)日：2023-04-20

申请号：US17836142

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L23/544 ,  H01L23/528 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.

公开(公告)号：US11569201B2

公开(公告)日：2023-01-31

申请号：US17509750

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Ji Hwang Kim ,  Jisun Yang ,  Seunghoon Yeon ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.