公开(公告)号：US20240203973A1

公开(公告)日：2024-06-20

申请号：US18591089

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakchul Jung ,  Ingyum Kim ,  Giyoung Yang ,  Jaewoo Seo

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

公开(公告)号：USRE49780E1

公开(公告)日：2024-01-02

申请号：US16916419

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong Song ,  Sanghoon Baek ,  Sungwe Cho ,  Jung-Ho Do ,  Giyoung Yang ,  Jinyoung Lim

IPC: H01L27/02 ,  H01L27/118 ,  G06F30/394

CPC classification number: G06F30/394 ,  H01L27/0207 ,  H01L27/11807

Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

公开(公告)号：US20230359797A1

公开(公告)日：2023-11-09

申请号：US18224337

申请日：2023-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyoung Yang ,  Ingyum Kim

IPC: G06F30/392 ,  G06F30/396 ,  H01L27/088

CPC classification number: G06F30/392 ,  G06F30/396 ,  H01L27/0886

Abstract: A semiconductor device includes a substrate having an active region, first standard cells arranged in a first row on the active region, second standard cells arranged in a second row on the active region and having a first boundary with the first standard cells, a third standard cells arranged in a third row on the active region and having a second boundary with the first standard cells, and a plurality of power supply lines, respectively arranged along boundaries. Each of the first to third standard cells includes a plurality of fin patterns extending in the first direction, and the plurality of fin patterns are arranged in a second direction, so as not to be disposed on at least one boundary, among the first and second boundaries.

公开(公告)号：US11741285B2

公开(公告)日：2023-08-29

申请号：US17361854

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyoung Yang ,  Ingyum Kim

IPC: G06F30/392 ,  G06F30/396 ,  H01L27/088

CPC classification number: G06F30/392 ,  G06F30/396 ,  H01L27/0886

Abstract: A semiconductor device includes a substrate having an active region, first standard cells arranged in a first row on the active region, second standard cells arranged in a second row on the active region and having a first boundary with the first standard cells, a third standard cells arranged in a third row on the active region and having a second boundary with the first standard cells, and a plurality of power supply lines, respectively arranged along boundaries. Each of the first to third standard cells includes a plurality of fin patterns extending in the first direction, and the plurality of fin patterns are arranged in a second direction, so as not to be disposed on at least one boundary, among the first and second boundaries.

公开(公告)号：US20220310586A1

公开(公告)日：2022-09-29

申请号：US17528242

申请日：2021-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakchul Jung ,  Ingyum Kim ,  Giyoung Yang ,  Jaewoo Seo

IPC: H01L27/02

Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

公开(公告)号：US09646960B2

公开(公告)日：2017-05-09

申请号：US15046200

申请日：2016-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Baek ,  Jung-Ho Do ,  Taejoong Song ,  Giyoung Yang ,  Seungyoung Lee ,  Jinyoung Lim

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1104

Abstract: A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.