公开(公告)号：US20240321735A1

公开(公告)日：2024-09-26

申请号：US18601467

申请日：2024-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungbo KO ,  Sujin KANG ,  Jongmin KIM ,  Donghyuk AHN ,  Jiwon OH ,  Chansic YOON ,  Myeongdong LEE ,  Minyoung LEE ,  Inho CHA

IPC: H01L23/528 ,  H10B12/00

CPC classification number: H01L23/528 ,  H10B12/00

Abstract: A semiconductor device includes a substrate, a word line extending on the substrate in a first horizontal direction, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate, and the spacer structure includes a depletion stopping layer on one sidewall of the lower conductive layer, extending in the vertical direction and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer, and an inner spacer extending in the vertical direction and on one sidewall of the depletion stopping layer.

公开(公告)号：US20240290833A1

公开(公告)日：2024-08-29

申请号：US18537552

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho CHOI ,  Kiseok LEE ,  Chansic YOON ,  Jaybok CHOI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/7855 ,  H10B12/482

Abstract: A semiconductor device includes device isolation layers extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction, active regions between the device isolation layers and spaced apart from each other in the first horizontal direction, insulating structures between the active regions, and a gate structure extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the active regions, wherein two side surfaces of each active region adjacent to each other define an acute angle, and wherein at least a portion of at least one of the insulating structures is between a corresponding pair of the active regions and between a corresponding pair of the device isolation layers and overlaps the corresponding pair of the active regions in the first horizontal direction.

公开(公告)号：US20230247826A1

公开(公告)日：2023-08-03

申请号：US18099302

申请日：2023-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyebin CHOI ,  Chansic YOON ,  Gyuhyun KIL

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes an active region, a gate dielectric layer disposed on the active region, a gate electrode disposed on the gate dielectric layer, a protective layer in contact with a portion of a side surface of the gate electrode, and a spacer structure covering the side surface of the gate electrode and the protective layer. The gate electrode includes a lower conductive pattern disposed on the gate dielectric layer, an intermediate conductive pattern disposed on the lower conductive pattern, and an upper conductive pattern disposed on the intermediate conductive pattern. The protective layer includes a first protective portion in contact with at least a portion of a side surface of the intermediate conductive pattern and a second protective portion in contact with a side surface of the upper conductive pattern, and the second protective portion includes a material different from a material of the first protective portion.