公开(公告)号：US20240321735A1

公开(公告)日：2024-09-26

申请号：US18601467

申请日：2024-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungbo KO ,  Sujin KANG ,  Jongmin KIM ,  Donghyuk AHN ,  Jiwon OH ,  Chansic YOON ,  Myeongdong LEE ,  Minyoung LEE ,  Inho CHA

IPC: H01L23/528 ,  H10B12/00

CPC classification number: H01L23/528 ,  H10B12/00

Abstract: A semiconductor device includes a substrate, a word line extending on the substrate in a first horizontal direction, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate, and the spacer structure includes a depletion stopping layer on one sidewall of the lower conductive layer, extending in the vertical direction and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer, and an inner spacer extending in the vertical direction and on one sidewall of the depletion stopping layer.