公开(公告)号：US20240321735A1

公开(公告)日：2024-09-26

申请号：US18601467

申请日：2024-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungbo KO ,  Sujin KANG ,  Jongmin KIM ,  Donghyuk AHN ,  Jiwon OH ,  Chansic YOON ,  Myeongdong LEE ,  Minyoung LEE ,  Inho CHA

IPC: H01L23/528 ,  H10B12/00

CPC classification number: H01L23/528 ,  H10B12/00

Abstract: A semiconductor device includes a substrate, a word line extending on the substrate in a first horizontal direction, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate, and the spacer structure includes a depletion stopping layer on one sidewall of the lower conductive layer, extending in the vertical direction and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer, and an inner spacer extending in the vertical direction and on one sidewall of the depletion stopping layer.

公开(公告)号：US20240179893A1

公开(公告)日：2024-05-30

申请号：US18216745

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu SUN ,  Hyunyong KIM ,  Hyun-Jung KIM ,  Junhee PARK ,  Kyuwon WOO ,  Jiwon OH ,  Yoonyoung CHOI

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device includes a substrate that includes an element separation film, an active region defined by the element separation film and arranged in a first direction, and a trench positioned across the active region and the element separation film, a bit line contact that is positioned within the trench and is connected to the active region, a bit line structure that is connected to the substrate through the bit line contact and that extends in a second direction different from the first direction across the active region, and a first contact spacer, a second contact spacer, and a third contact spacer within the trench and around the bit line contact, the first contact spacer being continuous within the trench, and each of the second contact spacer and the third contact spacer being separated into at least two discrete parts within the trench.

公开(公告)号：US20240096991A1

公开(公告)日：2024-03-21

申请号：US18219232

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun LIM ,  Subin KIM ,  Jiwon OH ,  Jinho PARK ,  Joongwon JEON

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/775

CPC classification number: H01L29/42376 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including first and second regions; a first active fin extending in a first direction on the first region; a second active fin extending in the first direction on the second region; an isolation pattern on the substrate between the first and second regions; a first gate structure on the first active fin, extending in a second direction perpendicular to the first direction, and onto an upper surface of the isolation pattern; and a second gate structure on the second active fin, extending in the second direction, and onto the upper surface of the isolation pattern, wherein the first gate structure includes a first portion having a first width and a second portion having a second width that is less than the first width, and the second gate structure includes a third portion having the first width and a fourth portion having the second width.