公开(公告)号：US20250040129A1

公开(公告)日：2025-01-30

申请号：US18655731

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungbo KO ,  Inwoo KIM ,  Jongmin KIM ,  Kiseok LEE ,  Minyoung LEE ,  Seongtak CHO ,  Inho CHA

IPC: H10B12/00

Abstract: A semiconductor device may include a device isolation layer on a side of the active region, a gate trench intersecting the active region, a gate structure in the gate trench, a bit line electrically connected to a first region of the active region, and a pad pattern electrically connected to a second region of the active region. An upper surface of the second region may be higher than an upper surface of the first region and lower than an upper surface of the bit line. A width of the bit line may be greater in an upper region than a lower region thereof. The pad pattern may contact upper and side surfaces of the second region. An upper surface of the pad pattern may be higher than an upper surface of the bit line. The gate trench may be between the first and second regions of the active region.

公开(公告)号：US20250040123A1

公开(公告)日：2025-01-30

申请号：US18665984

申请日：2024-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin KIM ,  Seungbo KO ,  Kiseok LEE

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the substrate, the gate structure extending across the active region in a first horizontal direction, bit line structures on bit line trenches extending in a second horizontal direction, intersecting the first horizontal direction, the bit line trenches on an upper surface of the substrate across the gate structure, contact plugs between the bit line structures, landing pad structures on the contact plugs, and an insulating pattern between the landing pad structures, the insulating pattern in contact with the bit line structures. Portions of the bit line structures extend in the second horizontal direction in the bit line trenches. Each of the landing pad structures includes a lower landing pad, arranged on a level lower than that of each of upper surfaces of the bit line structures, and an upper landing pad on the lower landing pad.

公开(公告)号：US20250063725A1

公开(公告)日：2025-02-20

申请号：US18656933

申请日：2024-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin KIM ,  Seungbo KO ,  Donghyuk AHN ,  Minyoung LEE

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device may include first and second bit lines that each include a line portion, a connection portion extending from the line portion into a first extension region, and a pad portion extending from the connection portion in the first extension region; and a third bit line between the line portions of the first and second bit lines in a memory cell array region and the first extension region. A first end portion of the third bit line may be in the first extension region. The pad portions of the first and second bit lines each may be wider than the line portions of the first and second bit lines. A minimum distance between the pad portions of the first and second bit lines may be less than a minimum distance between the line portion of the first bit line and the third bit line.

公开(公告)号：US20240321735A1

公开(公告)日：2024-09-26

申请号：US18601467

申请日：2024-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungbo KO ,  Sujin KANG ,  Jongmin KIM ,  Donghyuk AHN ,  Jiwon OH ,  Chansic YOON ,  Myeongdong LEE ,  Minyoung LEE ,  Inho CHA

IPC: H01L23/528 ,  H10B12/00

CPC classification number: H01L23/528 ,  H10B12/00

Abstract: A semiconductor device includes a substrate, a word line extending on the substrate in a first horizontal direction, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate, and the spacer structure includes a depletion stopping layer on one sidewall of the lower conductive layer, extending in the vertical direction and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer, and an inner spacer extending in the vertical direction and on one sidewall of the depletion stopping layer.