公开(公告)号：US20250040129A1

公开(公告)日：2025-01-30

申请号：US18655731

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungbo KO ,  Inwoo KIM ,  Jongmin KIM ,  Kiseok LEE ,  Minyoung LEE ,  Seongtak CHO ,  Inho CHA

IPC: H10B12/00

Abstract: A semiconductor device may include a device isolation layer on a side of the active region, a gate trench intersecting the active region, a gate structure in the gate trench, a bit line electrically connected to a first region of the active region, and a pad pattern electrically connected to a second region of the active region. An upper surface of the second region may be higher than an upper surface of the first region and lower than an upper surface of the bit line. A width of the bit line may be greater in an upper region than a lower region thereof. The pad pattern may contact upper and side surfaces of the second region. An upper surface of the pad pattern may be higher than an upper surface of the bit line. The gate trench may be between the first and second regions of the active region.