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    Semi-dense depth estimation from a dynamic vision sensor (DVS) stereo pair and a pulsed speckle pattern projector
    12.
    发明授权
    Semi-dense depth estimation from a dynamic vision sensor (DVS) stereo pair and a pulsed speckle pattern projector 有权

    公开(公告)号：US11143879B2

    公开(公告)日：2021-10-12

    申请号：US16172473

    申请日：2018-10-26

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Michael Sapienza ,  Ankur Gupta ,  Abhijit Bendale

    IPC: G02B27/48 ,  G06T19/00 ,  G03B21/20 ,  G06T7/50 ,  G06T7/521 ,  G06T7/593

    Abstract: A method for semi-dense depth estimation includes receiving, at an electronic device, a control signal of a speckle pattern projector (SPP and receiving from each sensor of a dynamic vision sensor (DVS) stereo pair, an event stream of pixel intensity change data, wherein the event stream is time-synchronized with the control signal of the SPP. The method further includes performing projected light filtering on the event stream of pixel intensity change data for each sensor of the DVS stereo pair, to generate synthesized event image data, the synthesized event image data having one or more channels, each channel based on an isolated portion of the event stream of pixel intensity change data and performing stereo matching on at least one channel of the synthesized event image data for each sensor of the DVS stereo pair to generate a depth map for at least a portion of the field of view.

    Bitline precharge system for a semiconductor memory device
    13.
    发明授权
    Bitline precharge system for a semiconductor memory device 有权

    公开(公告)号：US11776623B2

    公开(公告)日：2023-10-03

    申请号：US17815003

    申请日：2022-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Lava Kumar Pulluru ,  Ankur Gupta ,  Parvinder Kumar Rana

    IPC: G11C11/419

    CPC classification number: G11C11/419

    Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

    Camera pose and plane estimation using active markers and a dynamic vision sensor
    14.
    发明授权
    Camera pose and plane estimation using active markers and a dynamic vision sensor 有权

    公开(公告)号：US10529074B2

    公开(公告)日：2020-01-07

    申请号：US15962841

    申请日：2018-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Fannie Fontanel ,  Ankur Gupta ,  Michael Sapienza ,  Abhijit Z. Bendale ,  Pranav Mistry

    IPC: G06T7/73 ,  G06T7/20

    Abstract: A method of camera pose and plane estimation may include detecting a marker within a 3-dimensional (3D) environment by detecting, using a Dynamic Vision Sensor (DVS), a first plurality of light sources arranged in a known shape and blinking at a first frequency, wherein the known shape corresponds to the marker, determining an orientation and an identity of the marker based upon detecting, using the DVS, a second plurality of light sources corresponding to the marker and blinking at a second frequency different from the first frequency. A camera pose for the DVS may be determined based upon the known shape, the orientation, and the identity of the marker using the processor.

    Method and system for controller hold-margin of semiconductor memory device
    15.
    发明授权
    Method and system for controller hold-margin of semiconductor memory device 有权

    公开(公告)号：US10283177B1

    公开(公告)日：2019-05-07

    申请号：US16116615

    申请日：2018-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Lava Kumar Pulluru ,  Ankur Gupta

    IPC: H03H11/26 ,  G11C7/00 ,  G11C7/22 ,  H03K5/15 ,  G11C7/10 ,  H03K5/00

    Abstract: A system for controlling a hold-margin in a semiconductor memory device includes a programmable RC network communicatively coupled to a delay logic circuit, a latch clock generator and a latch circuit. A delay associated with a clock path is induced using a combination of a logic circuit and a wire placed across at least one of a column and a row of the semiconductor memory device. A delay associated with the data path is induced using a combination of the delay logic circuit and at least one of the load cell and a wire routed across at least one of a column and a row of the semiconductor memory device. The system controls the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

    Methods and systems for performing decoding in finFET based memories
    19.
    发明授权
    Methods and systems for performing decoding in finFET based memories 审中-公开

    公开(公告)号：US10672443B2

    公开(公告)日：2020-06-02

    申请号：US16166647

    申请日：2018-10-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ankur Gupta ,  Abhishek Kesarwani ,  Parvinder Kumar Rana ,  Manish Chandra Joshi ,  Lava Kumar Pulluru

    IPC: G11C8/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08 ,  G11C17/12 ,  G11C11/418 ,  G11C11/417

    Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

    SEMANTIC MAPPING FOR LOW-POWER AUGMENTED REALITY USING DYNAMIC VISION SENSOR
    20.
    发明申请
    SEMANTIC MAPPING FOR LOW-POWER AUGMENTED REALITY USING DYNAMIC VISION SENSOR 审中-公开

    公开(公告)号：US20190355169A1

    公开(公告)日：2019-11-21

    申请号：US16415860

    申请日：2019-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Michael Sapienza ,  Ankur Gupta ,  Abhijit Bendale ,  Fannie Fontanel

    IPC: G06T15/10 ,  H04N5/374 ,  G06T19/00 ,  G06T15/00 ,  G06T7/11 ,  G06K9/62

    Abstract: An apparatus includes a dynamic vision sensor (DVS) configured to output an asynchronous stream of sensor event data, a CMOS image sensor configured to output frames of image data, an inertial measurement unit (IMU), a processor and a memory. The memory contains instructions, which when executed by the processor, cause the apparatus to generate a semantic segmentation of a time-stamped frame, which is based on one or more of an output of the CMOS image sensor, or a synthesized event frame based on an output from the DVS and an output from the IMU over a time interval. The semantic segmentation includes a semantic label associated with a region of the time-stamped frame. When executed, the instructions further cause the apparatus to determine, based on the semantic segmentation, a simplified object representation in a coordinate space, and update a stable semantic map based on the simplified object representation.

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