Abstract:
An organic light-emitting display apparatus includes: a power voltage generation unit configured to generate a first power voltage and a dummy power voltage having a different level from that of the first power voltage; a power voltage wiring network to which the first power voltage is applied; a dummy power voltage line to which the dummy power voltage is applied; a plurality of pixels each comprising an emission device and a pixel circuit electrically coupled to the power voltage wiring network; a plurality of dummy pixels each comprising a dummy circuit connectable to the dummy power voltage line; and a plurality of repair lines each connectable to the dummy circuit of a corresponding dummy pixel among the plurality of dummy pixels and to the emission devices of corresponding pixels among the plurality of pixels.
Abstract:
An organic light emitting display device employing organic light emitting diodes (OLEDs) is disclosed. One aspect includes a plurality of pixels positioned at intersection portions of scan lines and data lines, each having an organic light emitting diode and a pixel circuit driving the organic light emitting diode; a scan driver supplying a scan signal to the scan lines and supplying an emission control signal to an emission control line coupled to the pixels; and a data driver supplying a data signal to the data lines. In such organic light emitting display, the pixel circuit within each pixel includes three or more transistors and one or more capacitors, and the transistors included in a pixel circuit of some of the pixels is formed to be in a state in which the transistor is isolated from the other circuit devices in the pixel circuit or in a state in which the electrodes of the transistor are short-circuited.
Abstract:
The present disclosure relates to a light emitting diode display device, and a light emitting diode display device according to an exemplary embodiment includes: a substrate; a semiconductor disposed on the substrate; a gate electrode disposed on the semiconductor; an interlayer insulating layer disposed on the substrate and the gate electrode; source and drain electrodes disposed on the interlayer insulating layer and connected to the semiconductor; a first slit provided in the interlayer insulating layer; and a first wire disposed on the interlayer insulating layer and configured to overlap the first slit.
Abstract:
A display panel is disclosed. The display panel includes a substrate, a plurality of first unit pixel and a plurality of second unit pixel. The substrate includes a first region and a second region extending in a first direction. The plurality of first unit pixels is disposed in the first region of the substrate. The first unit pixel has a first area. The plurality of second unit pixel is disposed in the second region of the substrate. The second unit pixel has a second area which is smaller than the first area.
Abstract:
A display device and a method of manufacturing the display device. The display device includes: a first substrate including a display region at which pixels are located; a second substrate on the first substrate while covering the display region; a sealant between the first substrate and the second substrate and surrounding the display region; and at least one protruding pattern located at an outer side of the sealant with respect to a center of the first substrate or the second substrate, on at least one of the first substrate or the second substrate.
Abstract:
A display device and a method of manufacturing the display device. The display device includes: a first substrate including a display region at which pixels are located; a second substrate on the first substrate while covering the display region; a sealant between the first substrate and the second substrate and surrounding the display region; and at least one protruding pattern located at an outer side of the sealant with respect to a center of the first substrate or the second substrate, on at least one of the first substrate or the second substrate.
Abstract:
A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.
Abstract:
A display substrate includes a gate line, a data line, a pixel electrode, a storage line, a dual transistor, a connection transistor, a voltage-decreasing electrode, a first contact electrode and a second contact electrode. The voltage-decreasing electrode is disposed on the storage line. The voltage-decreasing electrode is connected to a connection drain electrode of the connection transistor. The first contact electrode overlaps with the first pixel part and is electrically connected to the first pixel part. The first contact electrode is connected to a first drain electrode of the dual transistor and a connection source electrode of the connection transistor. The second contact electrode overlaps with the second pixel part and is electrically connected to the second pixel part. The second contact electrode is connected to a second drain electrode of the dual transistor. Therefore, the aperture ratio of the display device may be increased.
Abstract:
A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.