公开(公告)号：US09478667B2

公开(公告)日：2016-10-25

申请号：US14661470

申请日：2015-03-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yeon Keon Moon ,  Masataka Kano ,  Sung-Hoon Yang ,  Ji Hun Lim ,  So Young Koo ,  Myoung Hwa Kim ,  Jun Hyung Lim

IPC: G02F1/136 ,  G02F1/1333 ,  H01L29/786 ,  H01L29/66 ,  G02F1/1368

CPC classification number: H01L29/78645 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78648

Abstract: A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.

Abstract translation: 薄膜晶体管衬底包括衬底，衬底上的底栅，衬底上的第一绝缘层和底栅，第一绝缘层上的漏极，第一绝缘层上的源，源包括第一绝缘层 漏极的第一侧的源极和在漏极的第二侧的第二源极，在第一绝缘层上的有源层，有源层包括接触漏极和第一源极的第一有源层和与第一源极接触的第二有源层 漏极和第二源极，漏极，源极和有源层上的第二绝缘层，以及第二绝缘层上的顶栅极。

公开(公告)号：US10985281B2

公开(公告)日：2021-04-20

申请号：US16752126

申请日：2020-01-24

Applicant: Samsung Display Co., Ltd.

Inventor： Ji Hun Lim ,  Joon Seok Park ,  Jay Bum Kim ,  Jun Hyung Lim ,  Kyoung Seok Son

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423

Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.

公开(公告)号：US10396101B2

公开(公告)日：2019-08-27

申请号：US16241247

申请日：2019-01-07

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji Hun Lim ,  Joon Seok Park

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

公开(公告)号：US09553201B2

公开(公告)日：2017-01-24

申请号：US14179452

申请日：2014-02-12

Applicant: Samsung Display Co., Ltd. ,  Kobe Steel, Ltd.

Inventor： Byung Du Ahn ,  Ji Hun Lim ,  Gun Hee Kim ,  Kyoung Won Lee ,  Je Hun Lee ,  Hiroshi Goto ,  Aya Miki ,  Shinya Morita ,  Toshihiro Kugimiya ,  Yeon Hong Kim ,  Yeon Gon Mo ,  Kwang Suk Kim

IPC: H01L27/14 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78696

Abstract: The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

Abstract translation: 本发明构思涉及薄膜晶体管和薄膜晶体管阵列面板，并且详细地涉及包括氧化物半导体的薄膜晶体管。 根据本发明构思的示例性实施例的薄膜晶体管包括：栅电极; 位于栅极电极上或下方的栅极绝缘层; 第一半导体和第二半导体，其与栅电极重叠，栅极绝缘层插入其间，第一半导体和第二半导体彼此接触; 连接到所述第二半导体的源电极; 和连接到第二半导体并面向源电极的漏电极，其中第二半导体包括不包括在第一半导体中的镓（Ga），并且第二半导体中的镓（Ga）的含量大于0 。 ％且小于或等于约33at。 ％。

公开(公告)号：US09257563B2

公开(公告)日：2016-02-09

申请号：US13798811

申请日：2013-03-13

Applicant: Samsung Display Co., Ltd. ,  Kookmin University Industry Academy Cooperation Foundation

Inventor： Byung Du Ahn ,  Jung Hwa Kim ,  Ji Hun Lim ,  Je Hun Lee ,  Dae Hwan Kim ,  Hyun Kwang Jung

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L33/38 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78693 ,  H01L33/387

Abstract: A thin film transistor array panel includes a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode and a drain electrode on the semiconductor layer and facing each other, a floating metal layer between the source electrode and the drain electrode, and a passivation layer covering the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floating.

Abstract translation: 薄膜晶体管阵列面板包括基板，基板上的栅极电极，栅电极上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层上的源电极和漏电极，并面对彼此 ，源电极和漏电极之间的浮动金属层，以及覆盖源电极，漏电极和浮置金属层的钝化层。 浮动金属层电浮动。

公开(公告)号：US08969872B2

公开(公告)日：2015-03-03

申请号：US13789335

申请日：2013-03-07

Applicant: Samsung Display Co., Ltd.

Inventor： Byung Du Ahn ,  Ji Hun Lim ,  Jun Hyung Lim ,  Dae Hwan Kim ,  Jae Hyeong Kim ,  Je Hun Lee ,  Hyun Kwang Jung

IPC: H01L29/04 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/78606 ,  H01L21/28 ,  H01L27/124 ,  H01L29/786 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.

Abstract translation: 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。