公开(公告)号：US09640566B2

公开(公告)日：2017-05-02

申请号：US14487300

申请日：2014-09-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

IPC: G02F1/136 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  G02F1/1343 ,  G02F1/1362

CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

公开(公告)号：US09405156B2

公开(公告)日：2016-08-02

申请号：US13938106

申请日：2013-07-09

Applicant: Samsung Display Co., Ltd.

Inventor： Yong-Hwan Ryu ,  Sang Gab Kim ,  Hong Sick Park ,  Jung Ha Son ,  Shin Il Choi

IPC: G02F1/1341 ,  G02F1/1333

CPC classification number: G02F1/1341 ,  G02F1/133345

Abstract: A liquid crystal display is provided. The liquid crystal display includes a substrate, a thin film transistor disposed on the substrate, a pixel electrode connected with a terminal of the thin film transistor, a microcavity disposed on the pixel electrode, the microcavity including a liquid crystal injection hole disposed at an edge of the microcavity, a supporting member disposed on the microcavity, a first hydrophobic layer disposed on an edge portion of the supporting member, and a capping layer disposed on the supporting member with the capping layer covering the liquid crystal injection hole.

Abstract translation: 提供液晶显示器。 液晶显示器包括基板，设置在基板上的薄膜晶体管，与薄膜晶体管的端子连接的像素电极，设置在像素电极上的微腔，微腔包括设置在边缘的液晶注入孔 设置在所述微腔上的支撑构件，设置在所述支撑构件的边缘部分上的第一疏水层和设置在所述支撑构件上的覆盖层，所述覆盖层覆盖所述液晶注入孔。

公开(公告)号：US20160190186A1

公开(公告)日：2016-06-30

申请号：US14992625

申请日：2016-01-11

Applicant: Samsung Display Co., Ltd.

Inventor： Hong-Kee Chin ,  Yun Jong Yeo ,  Sang Gab Kim ,  Jung Suk Bang ,  Byeong Hoon Cho

IPC: H01L27/144 ,  H01L31/0376 ,  H01L31/20 ,  H01L31/113

CPC classification number: H01L27/1288 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1218 ,  H01L27/1251 ,  H01L27/127 ,  H01L27/1446 ,  H01L31/03765 ,  H01L31/1136 ,  H01L31/204

Abstract: A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is disposed on the substrate and includes a stepped portion. The first semiconductor is disposed on the insulation layer. The second semiconductor is disposed on the insulation layer and includes a semiconductor material different than the first semiconductor. The stepped portion is spaced apart from an edge of the first semiconductor.

Abstract translation: 薄膜晶体管阵列面板包括基板，绝缘层，第一半导体和第二半导体。 绝缘层设置在基板上并且包括台阶部分。 第一半导体设置在绝缘层上。 第二半导体设置在绝缘层上，并且包括与第一半导体不同的半导体材料。 台阶部分与第一半导体的边缘间隔开。

公开(公告)号：US09379252B2

公开(公告)日：2016-06-28

申请号：US14666461

申请日：2015-03-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US08987047B2

公开(公告)日：2015-03-24

申请号：US14184361

申请日：2014-02-19

Applicant: Samsung Display Co., Ltd.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L21/00 ,  H01L29/10 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US12087865B2

公开(公告)日：2024-09-10

申请号：US18176454

申请日：2023-02-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H10K59/121

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H10K59/1213

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US11937472B2

公开(公告)日：2024-03-19

申请号：US17445471

申请日：2021-08-19

Applicant: Samsung Display Co., Ltd. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Sang Gab Kim ,  Hyun Min Cho ,  Tae Sung Kim ,  Yu-Gwang Jeong ,  Su Bin Bae ,  Jin Seock Kim ,  Sang Gyun Kim ,  Hyo Min Ko ,  Kil Won Cho ,  Hansol Lee

IPC: H10K59/131 ,  H10K59/12 ,  H10K71/00 ,  H10K102/00

CPC classification number: H10K59/131 ,  H10K59/1201 ,  H10K71/00 ,  H10K2102/341

Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.

公开(公告)号：US11380753B2

公开(公告)日：2022-07-05

申请号：US16899782

申请日：2020-06-12

Applicant: Samsung Display Co., LTD.

Inventor： Sang Gab Kim ,  Tae Sung Kim ,  Joon Geol Lee ,  Hyun Min Cho ,  Dae Won Choi ,  Yun Jong Yeo

IPC: H01L27/32 ,  H01L51/00

Abstract: A display device includes a base substrate; an organic layer disposed on the base substrate; and a first conductive layer disposed on the organic layer, wherein the first conductive layer includes a plurality of stacked films, the plurality of stacked films include a first conductive film disposed directly on the organic layer and a second conductive film disposed on the first conductive film, and the first conductive film has an oxygen concentration higher than an oxygen concentration of the second conductive film.

公开(公告)号：US11189681B2

公开(公告)日：2021-11-30

申请号：US16409991

申请日：2019-05-13

Applicant: Samsung Display Co., Ltd.

Inventor： Kyeong Su Ko ,  Joon Geol Lee ,  Shin Il Choi ,  Sang Gab Kim ,  Hyun Min Cho ,  Hyun Eok Shin

IPC: H01L51/05 ,  H01L51/00 ,  H01L27/32 ,  H01L51/56

Abstract: An OLED display according to an exemplary embodiment includes: a substrate; a gate insulation layer that is disposed on the substrate; and a gate wire that is disposed on the gate insulation layer, and includes a gate electrode, wherein the gate wire includes a single layer of aluminum or an aluminum alloy, and an angle formed by side surfaces of the gate wire and the gate insulation layer is less than 65°.

公开(公告)号：US11183518B2

公开(公告)日：2021-11-23

申请号：US16987952

申请日：2020-08-07

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang Jeong ,  Hyun Min Cho ,  Su Bin Bae ,  Shin Il Choi ,  Sang Gab Kim

IPC: H01L27/12 ,  H01L21/311 ,  H01L29/417 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/32

Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.