公开(公告)号：US09716048B2

公开(公告)日：2017-07-25

申请号：US14985379

申请日：2015-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek ,  Seokhyun Lee

IPC: H01L21/66

CPC classification number: H01L22/32 ,  H01L21/76877 ,  H01L21/822 ,  H01L22/14 ,  H01L22/34 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10897

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

公开(公告)号：US09553074B2

公开(公告)日：2017-01-24

申请号：US14732660

申请日：2015-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho

IPC: H01L23/40 ,  H01L25/11 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/4012 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05554 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06135 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/92163 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: A semiconductor package that includes a package substrate, a lower semiconductor chip mounted on the package substrate, and an upper semiconductor chip stacked on the lower semiconductor chip in a cascade shape is provided. An active surface of the lower semiconductor chip is facing an active surface of the upper semiconductor chip.

Abstract translation: 提供一种半导体封装，其包括封装基板，安装在封装基板上的下部半导体芯片和层叠在下部半导体芯片上的上部半导体芯片。 下半导体芯片的有源表面面向上半导体芯片的有源表面。

公开(公告)号：US20250157960A1

公开(公告)日：2025-05-15

申请号：US18937941

申请日：2024-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho CHA ,  Yun-Rae Cho

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes: a first semiconductor chip having a first region and a second region contacting the first region; and a second semiconductor chip on a top surface of the first semiconductor chip, wherein the first semiconductor chip includes: a first pad in the first region and on the top surface of the first semiconductor chip, the first pad comprising a first pad portion and a first protrusion protruding from a top surface of the first pad portion; and a second pad in the second region and on the top surface of the first semiconductor chip and having a flat top surface.

公开(公告)号：US20240088082A1

公开(公告)日：2024-03-14

申请号：US18229446

申请日：2023-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho Cha ,  Yun-Rae Cho

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L23/5228 ,  H01L23/544 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17133 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/3511

Abstract: A semiconductor package, including a substrate extending in first direction and a second direction intersecting the first direction and including a solder resist layer having an open area thereon; a semiconductor chip on the substrate in a third direction, the third direction intersecting the first direction and the second direction, a first surface of the semiconductor chip facing the substrate; and a bump structure in contact with a first connection pad on the open area and a second connection pad on the first surface of the semiconductor chip, and configured to connect the substrate to the semiconductor chip, wherein the open area includes a first area and a second area disposed in a peripheral part of the first area, and wherein a length of the first area in the first direction is greater than a length of the second area in the first direction.

公开(公告)号：US10950586B2

公开(公告)日：2021-03-16

申请号：US16437595

申请日：2019-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho

IPC: H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of the package substrate. The solder bump includes a core portion and a peripheral portion encapsulating the core portion. The peripheral portion includes a first segment with a first melting point and a second segment with a second melting point that is less than the first melting point.

公开(公告)号：US10559543B2

公开(公告)日：2020-02-11

申请号：US16024309

申请日：2018-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/31

Abstract: A semiconductor device includes a substrate including a first region and a second region at least partially surrounding the first region in a plan view. A protection pattern is disposed on the second region of the substrate and at least partially surrounds the first region of the substrate in the plan view. A protection trench overlaps the protection pattern and at least partially surrounds the first region of the substrate in the plan view, along the protection pattern. A width of the protection trench is different from a width of the protection pattern.

公开(公告)号：US20170221866A1

公开(公告)日：2017-08-03

申请号：US15374392

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of the package substrate. The solder bump includes a core portion and a peripheral portion encapsulating the core portion. The peripheral portion includes a first segment with a first melting point and a second segment with a second melting point that is less than the first melting point.

公开(公告)号：US20170062293A1

公开(公告)日：2017-03-02

申请号：US15219457

申请日：2016-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Sun-Dae Kim ,  Nam-Gyu Baek ,  Hyung-Gil Baek

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/58

CPC classification number: H01L22/34 ,  G01R31/2856 ,  G01R31/2884 ,  H01L21/67288 ,  H01L23/585

Abstract: A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line. Thus, although a crack may be generated in the corner of the semiconductor substrate by twice cutting processes of a wafer, the crack detection circuit may not detect the crack.

Abstract translation: 半导体芯片可以包括半导体衬底和裂纹检测电路。 半导体衬底可以包括电路结构。 裂纹检测电路可以包括主线和倒角线。 主线可以形成在半导体衬底中以包围电路结构。 倒角线可以形成在半导体衬底的角部。 倒角线可以连接在主线之间。 可以在每个倒角线和彼此垂直的两个主线中的任一个之间形成第一角度。 可以在每个倒角线和另一个主线之间形成比第一角宽的第二角度。 因此，尽管通过两次切割晶片的过程可能在半导体基板的拐角处产生裂纹，但是裂纹检测电路可能不会检测到裂纹。

公开(公告)号：US20140008772A1

公开(公告)日：2014-01-09

申请号：US13803136

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/295 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include a wiring board including a mounting region and a ground region that surrounds the mounting region, a ground pad positioned at the ground region, at least one semiconductor chip mounted at the mounting region of the wiring board, a molding layer covering the semiconductor chip and a first surface of the wiring board and exposing a portion of the ground pad of the ground region of the wiring board, and a shield layer covering the molding layer and electrically connected to the ground pad. The molding layer comprises a plurality of light-sensitive particles positioned in the molding layer and a plurality of conductive particles positioned at a surface of the molding layer. The shield layer is in direct contact with the conductive particles.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括布线​​板，其包括安装区域和围绕安装区域的接地区域，位于接地区域的接地焊盘，安装在布线板的安装区域的至少一个半导体芯片，覆盖 所述半导体芯片和所述布线板的第一表面，并且暴露所述布线板的接地区域的接地焊盘的一部分，以及覆盖所述模制层并电连接到所述接地焊盘的屏蔽层。 模制层包括位于模制层中的多个感光颗粒和位于成型层表面的多个导电颗粒。 屏蔽层与导电颗粒直接接触。

公开(公告)号：US20130328177A1

公开(公告)日：2013-12-12

申请号：US13771609

申请日：2013-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L21/56 ,  H01L23/552

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。