公开(公告)号：US20240064974A1

公开(公告)日：2024-02-22

申请号：US18386639

申请日：2023-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ho AHN ,  Ji Won KIM ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H10B41/27 ,  H01L23/538 ,  H01L25/065 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L23/5384 ,  H01L25/0657 ,  H10B43/27

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

公开(公告)号：US20230005942A1

公开(公告)日：2023-01-05

申请号：US17678473

申请日：2022-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Jae-Joo SHIM ,  Dong-Sik LEE ,  Bongtae PARK

IPC: H01L27/11539 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

Abstract: A 3D semiconductor memory device includes a substrate, a stack structure comprising interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, vertical channel structures penetrating the stack structure, a separation structure spaced apart from the vertical channel structures and filling a trench crossing the stack structure, the separation structure comprising a spacer covering an inner sidewall of the trench, and a first conductive contact filling an inner space of the trench surrounded by the spacer, an insulating layer covering the substrate and the stack structure, contact plugs penetrating the insulating layer so as to be connected to the gate electrodes of the stack structure, and a second conductive contact spaced apart from the stack structure and penetrating the insulating layer so as to be connected to a peripheral circuit transistor. A bottom surface of the first conductive contact is at a level lower than a bottom surface of the spacer.

公开(公告)号：US20220123006A1

公开(公告)日：2022-04-21

申请号：US17340148

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ho AHN ,  Ji Won KIM ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H01L27/11556 ,  H01L25/065 ,  H01L27/11582 ,  H01L23/538

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

公开(公告)号：US20190198511A1

公开(公告)日：2019-06-27

申请号：US16283141

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Zhiliang XIA ,  Ahn-Sik MOON ,  Se-Jun PARK ,  Joon-Sung LIM ,  Sung-Min HWANG

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11582

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

公开(公告)号：US20190035808A1

公开(公告)日：2019-01-31

申请号：US16010743

申请日：2018-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min HWANG ,  Dong-Sik LEE ,  Joon-Sung LIM

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522

Abstract: A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.

公开(公告)号：US20220108963A1

公开(公告)日：2022-04-07

申请号：US17323076

申请日：2021-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min HWANG ,  Ji Won KIM ,  Jae Ho AHN ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

公开(公告)号：US20210391349A1

公开(公告)日：2021-12-16

申请号：US17460814

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung LIM ,  Eunsuk CHO

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11582 ,  H01L25/065 ,  H01L27/11575

Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

公开(公告)号：US20200152654A1

公开(公告)日：2020-05-14

申请号：US16514557

申请日：2019-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung LIM ,  Jiyoung KIM ,  Jiwon KIM ,  Woosung YANG

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern.

公开(公告)号：US20180358372A1

公开(公告)日：2018-12-13

申请号：US15989477

申请日：2018-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung Lim ,  Gilsung Lee ,  Eunsuk Cho

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/24

CPC classification number: H01L27/11573 ,  G11C16/24 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.

公开(公告)号：US20180358371A1

公开(公告)日：2018-12-13

申请号：US15982001

申请日：2018-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung LIM ,  Eunsuk CHO

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L25/065 ,  H01L29/66 ,  H01L27/11582 ,  H01L29/423

Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.