公开(公告)号：US20200135757A1

公开(公告)日：2020-04-30

申请号：US16437208

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

Abstract: A vertical memory device includes conductive lines on a substrate, first and second semiconductor patterns, first and second pads, first and second electrodes, a third electrode, and a first division pattern. The conductive lines are stacked in a vertical direction and extend in a first direction. The first and second semiconductor patterns extend through the conductive lines in the vertical direction. The first and second pads are formed on the first and second semiconductor patterns. The first and second electrodes are electrically connected to the first and second pads. The third electrode is electrically connected to a first conductive line of the conductive lines. The first division pattern extends in a second direction, and extends through and divides the first conductive line. In a plan view, the first and second semiconductor patterns and the first conductive line are disposed at one side of the first division pattern.

公开(公告)号：US20200295042A1

公开(公告)日：2020-09-17

申请号：US16889947

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Sung LIM ,  Jang-Gn YUN ,  Jaesun YUN

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

公开(公告)号：US20190051665A1

公开(公告)日：2019-02-14

申请号：US16165426

申请日：2018-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US20190198511A1

公开(公告)日：2019-06-27

申请号：US16283141

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Zhiliang XIA ,  Ahn-Sik MOON ,  Se-Jun PARK ,  Joon-Sung LIM ,  Sung-Min HWANG

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11582

Abstract: A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

公开(公告)号：US20210151467A1

公开(公告)日：2021-05-20

申请号：US17162526

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Sunghoi HUR ,  Jaesun YUN ,  Joon-Sung LIM

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US20190386019A1

公开(公告)日：2019-12-19

申请号：US16260368

申请日：2019-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Gn YUN ,  Jae-Duk LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311

Abstract: A vertical memory device includes a substrate having a trench structure, gate electrodes on the substrate, the gate electrodes being spaced apart from each other in a first direction substantially vertical to an upper surface of the substrate, a channel including a vertical portion extending through the gate electrodes in the first direction, and a horizontal portion extending in the trench structure in a second direction substantially parallel to the upper surface of the substrate, the horizontal portion being connected the vertical portion, and an epitaxial layer on a first portion of the substrate and connected to the horizontal portion of the channel, the first portion of the substrate being adjacent to ends of the gate electrode in the second direction.

公开(公告)号：US20180374867A1

公开(公告)日：2018-12-27

申请号：US15860082

申请日：2018-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Kyoil KOO ,  Hoosung CHO ,  Sunyoung KIM ,  Cheol RYOU ,  Jaesun YUN

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/4234

Abstract: Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.

公开(公告)号：US20150357339A1

公开(公告)日：2015-12-10

申请号：US14826814

申请日：2015-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil SHIM ,  Jang-Gn YUN ,  Jeonghyuk CHOI ,  Kwang Soo SEOL ,  Jaehoon JANG ,  Jungdal CHOI

IPC: H01L27/115 ,  H01L23/535

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

Abstract translation: 提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和 第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到 第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。

公开(公告)号：US20140159137A1

公开(公告)日：2014-06-12

申请号：US14177693

申请日：2014-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn YUN ,  Jung-Dal CHOI ,  Kwang-Soo SEOL

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

Abstract: A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.

Abstract translation: 非易失性存储器件的栅极结构及其形成方法，其包括隧道氧化物层图案，电荷陷阱层图案，阻挡介电层图案，其最上层包括第一介电常数大于其的介电常数的材料。 包括在隧道氧化物层图案中的材料，以及第一和第二导电层图案。 栅极结构包括至少覆盖第二导电层图案的侧壁的第一间隔物。 栅极结构包括覆盖第一间隔物的侧壁和第一导电层图案的侧壁的第二间隔物，并且包括具有等于或大于第一介电常数的第二介电常数的材料。 在包括栅极结构的非易失性存储器件中，由于后部隧道引起的擦除饱和度降低。