Abstract:
Magnetic memory cells include a magnetic tunnel junction and a first electrode, which is electrically coupled to the magnetic tunnel junction by a first conductive structure. This conductive structure includes a blocking layer and a seed layer, which extends between the blocking layer and the magnetic tunnel junction. The blocking layer is formed as an amorphous metal compound. In some of the embodiments, the blocking layer is a thermally treated layer and an amorphous state of the blocking layer is maintained during and post thermal treatment.
Abstract:
A magnetic memory device may include a substrate and a magnetic tunnel junction memory element on the substrate. The magnetic tunnel junction memory element may include a reference magnetic layer, a tunnel barrier layer, and a free magnetic layer. The reference magnetic layer may include a first pinned layer, an exchange coupling layer, and a second pinned layer. The exchange coupling layer may be between the first and second pinned layers, and the second pinned layer may include a ferromagnetic layer and a non-magnetic layer. The second pinned layer may be between the first pinned layer and the tunnel barrier layer, and the tunnel barrier layer may be between the reference magnetic layer and the free magnetic layer.
Abstract:
A semiconductor device includes a first transistor on a first region of a substrate, and a second transistor on a second region of the substrate. The first transistor includes a first gate insulating layer including a first interfacial insulating layer, a first lower high-κ dielectric layer, and a first composite dielectric layer, sequentially stacked on each of first semiconductor channel layers. The second transistor includes a second gate insulating layer including a second interfacial insulating layer, a second lower high-κ dielectric layer, a second composite dielectric layer, and a second upper high-κ dielectric layer, sequentially stacked on each of second semiconductor channel layers. The first and the second lower high-κ dielectric layers include a first metal element, the second upper high-κ dielectric layer includes a second metal element, and the first and the second composite dielectric layers include both of the first and the second metal elements.
Abstract:
A semiconductor device includes a first active region on a substrate, channel layers disposed on the first active region to be spaced apart from each other in a vertical direction, a first gate structure disposed on the first active region and surrounding each channel layer, and a first source/drain region on the first active region on at least one side of the first gate structure. The channel layers include first to third channel layers. The first gate structure includes a first gate electrode and a first gate dielectric layer. The first gate dielectric layer includes first to third portions surrounding the first to third channel layers, respectively. The second portion has a thickness greater than a thickness of the first portion, and the third portion has a thickness greater than the thickness of the second portion.
Abstract:
A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.
Abstract:
A method of controlling the output according to a type of connector and an electronic device adapted to the method are provided. The method includes determining whether a first, second and third external connector is inserted into a receptacle, via a circuit connected to the receptacle, wherein the receptacle is configured to receive the first, second or third external connector, each of the first and second connector includes a first number of contacts, and the third external connector includes a second number of contacts less than the first number of contacts; providing an audio output signal to the first external connector in a first manner when the first external connector is inserted into the receptacle; providing an audio output signal to the second external connector in a second manner which differs from the first manner when the second external connector is inserted into the receptacle; and providing an audio output signal to the third external connector in a third manner which differs from the first and second manners when the third external connector is inserted into the receptacle.
Abstract:
A method of controlling the output according to a type of connector and an electronic device adapted to the method are provided. The method includes determining whether a first, second and third external connector is inserted into a receptacle, via a circuit connected to the receptacle, wherein the receptacle is configured to receive the first, second or third external connector, each of the first and second connector includes a first number of contacts, and the third external connector includes a second number of contacts less than the first number of contacts; providing an audio output signal to the first external connector in a first manner when the first external connector is inserted into the receptacle; providing an audio output signal to the second external connector in a second manner which differs from the first manner when the second external connector is inserted into the receptacle; and providing an audio output signal to the third external connector in a third manner which differs from the first and second manners when the third external connector is inserted into the receptacle.