Memory devices and methods of manufacturing the same
    12.
    发明授权
    Memory devices and methods of manufacturing the same 有权
    存储器件及其制造方法

    公开(公告)号:US09184376B2

    公开(公告)日:2015-11-10

    申请号:US14315610

    申请日:2014-06-26

    CPC classification number: H01L43/10 G11C11/161 H01L43/08

    Abstract: A magnetic memory device may include a substrate and a magnetic tunnel junction memory element on the substrate. The magnetic tunnel junction memory element may include a reference magnetic layer, a tunnel barrier layer, and a free magnetic layer. The reference magnetic layer may include a first pinned layer, an exchange coupling layer, and a second pinned layer. The exchange coupling layer may be between the first and second pinned layers, and the second pinned layer may include a ferromagnetic layer and a non-magnetic layer. The second pinned layer may be between the first pinned layer and the tunnel barrier layer, and the tunnel barrier layer may be between the reference magnetic layer and the free magnetic layer.

    Abstract translation: 磁存储器件可以在衬底上包括衬底和磁性隧道结存储元件。 磁性隧道结存储元件可以包括参考磁性层,隧道势垒层和自由磁性层。 参考磁性层可以包括第一固定层,交换耦合层和第二固定层。 交换耦合层可以在第一和第二被钉扎层之间,并且第二被钉扎层可以包括铁磁层和非磁性层。 第二被钉扎层可以在第一被钉扎层和隧道势垒层之间,并且隧道势垒层可以在参考磁性层和自由磁性层之间。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20240145573A1

    公开(公告)日:2024-05-02

    申请号:US18382166

    申请日:2023-10-20

    Abstract: A semiconductor device includes a first transistor on a first region of a substrate, and a second transistor on a second region of the substrate. The first transistor includes a first gate insulating layer including a first interfacial insulating layer, a first lower high-κ dielectric layer, and a first composite dielectric layer, sequentially stacked on each of first semiconductor channel layers. The second transistor includes a second gate insulating layer including a second interfacial insulating layer, a second lower high-κ dielectric layer, a second composite dielectric layer, and a second upper high-κ dielectric layer, sequentially stacked on each of second semiconductor channel layers. The first and the second lower high-κ dielectric layers include a first metal element, the second upper high-κ dielectric layer includes a second metal element, and the first and the second composite dielectric layers include both of the first and the second metal elements.

    SEMICONDUCTOR DEVICE
    14.
    发明申请

    公开(公告)号:US20220238653A1

    公开(公告)日:2022-07-28

    申请号:US17513262

    申请日:2021-10-28

    Abstract: A semiconductor device includes a first active region on a substrate, channel layers disposed on the first active region to be spaced apart from each other in a vertical direction, a first gate structure disposed on the first active region and surrounding each channel layer, and a first source/drain region on the first active region on at least one side of the first gate structure. The channel layers include first to third channel layers. The first gate structure includes a first gate electrode and a first gate dielectric layer. The first gate dielectric layer includes first to third portions surrounding the first to third channel layers, respectively. The second portion has a thickness greater than a thickness of the first portion, and the third portion has a thickness greater than the thickness of the second portion.

    SEMICONDUCTOR DEVICES
    15.
    发明申请

    公开(公告)号:US20190081148A1

    公开(公告)日:2019-03-14

    申请号:US15938716

    申请日:2018-03-28

    Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

    METHOD AND APPARATUS FOR CONTROLLING OUTPUT BASED ON TYPE OF CONNECTOR
    17.
    发明申请
    METHOD AND APPARATUS FOR CONTROLLING OUTPUT BASED ON TYPE OF CONNECTOR 有权
    用于控制基于连接器类型的输出的方法和装置

    公开(公告)号:US20170026745A1

    公开(公告)日:2017-01-26

    申请号:US15215202

    申请日:2016-07-20

    Abstract: A method of controlling the output according to a type of connector and an electronic device adapted to the method are provided. The method includes determining whether a first, second and third external connector is inserted into a receptacle, via a circuit connected to the receptacle, wherein the receptacle is configured to receive the first, second or third external connector, each of the first and second connector includes a first number of contacts, and the third external connector includes a second number of contacts less than the first number of contacts; providing an audio output signal to the first external connector in a first manner when the first external connector is inserted into the receptacle; providing an audio output signal to the second external connector in a second manner which differs from the first manner when the second external connector is inserted into the receptacle; and providing an audio output signal to the third external connector in a third manner which differs from the first and second manners when the third external connector is inserted into the receptacle.

    Abstract translation: 提供了一种根据连接器类型和适用于该方法的电子设备来控制输出的方法。 该方法包括通过连接到插座的电路来确定第一,第二和第三外部连接器是否插入插座中,其中插座构造成接收第一,第二或第三外部连接器,第一和第二连接器中的每一个 包括第一数量的触点,并且第三外部连接器包括小于第一数量的触点的第二数量的触点; 当所述第一外部连接器插入所述插座时,以第一方式向所述第一外部连接器提供音频输出信号; 以第二种方式向第二外部连接器提供音频输出信号,当第二外部连接器插入插座时,该输出信号与第一方式不同; 以及以第三方式向第三外部连接器提供音频输出信号,当第三外部连接器插入插座时,该输出信号与第一和第二方式不同。

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