公开(公告)号：US20250125197A1

公开(公告)日：2025-04-17

申请号：US18884732

申请日：2024-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun Kweon ,  Wooju Kim ,  Junho Yoon ,  Dayoung Cho ,  Jinwook Hong

IPC: H01L21/78 ,  B23K26/38 ,  B23K101/40 ,  H01L21/02 ,  H01L21/304 ,  H01L21/683

Abstract: A semiconductor chip includes a base substrate including a first surface, a second surface opposite to the first surface, and a sidewall extending between the first surface and the second surface, and a device layer on the first surface of the base substrate, wherein the base substrate includes a stress relief region within a first depth from the second surface and a second depth from the sidewall, and at least a portion of the sidewall of the base substrate is recessed inward from the sidewall of the device layer.

公开(公告)号：US11322405B2

公开(公告)日：2022-05-03

申请号：US16909136

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Jungchul Lee ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim

IPC: G11B11/105 ,  B23K26/00 ,  B23K26/40 ,  H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  H01L21/304

Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.

公开(公告)号：US20220059472A1

公开(公告)日：2022-02-24

申请号：US17216279

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US20180090303A1

公开(公告)日：2018-03-29

申请号：US15400126

申请日：2017-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Jaehyun Lee

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/66 ,  G01N29/24 ,  G01N29/12

CPC classification number: H01J37/32935 ,  G01N29/12 ,  G01N29/2437 ,  H01J37/32568 ,  H01J37/3299 ,  H01J2237/334 ,  H01L21/3065 ,  H01L22/14 ,  H01L22/20

Abstract: A monitoring unit for monitoring a plasma process chamber includes a piezoelectric member comprising a surface that is exposed within the plasma process chamber, a first electrode coupled to the piezoelectric member, a power supply unit coupled to the first electrode and configured to apply a voltage to the piezoelectric member through the first electrode, and a control unit coupled to the piezoelectric member and configured to detect a vibration frequency of the piezoelectric member. The vibration frequency is generated in response to the voltage applied to the piezoelectric member.

公开(公告)号：US09123657B2

公开(公告)日：2015-09-01

申请号：US14326960

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjoon Park ,  Junho Yoon ,  Je-Woo Han ,  Chan-Won Kim

IPC: H01L21/76 ,  H01L21/308 ,  H01L49/02

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/31144 ,  H01L23/544 ,  H01L28/40 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayer insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayer insulating layer, forming trenches in the first mask layer exposing the interlayer insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayer insulating layer may be greater than that of the key mask patterns with respect to the interlayer insulating layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在具有单元区域和外围电路区域的结构上形成层间绝缘层，在层间绝缘层上形成第一掩模层，在第一掩模层中形成沟槽，通过图案化第一掩模 并且在沟槽中形成键掩模图案。 第一掩模图案相对于层间绝缘层的蚀刻选择性可以大于键层掩模图案相对于层间绝缘层的蚀刻选择性。

公开(公告)号：US08969167B2

公开(公告)日：2015-03-03

申请号：US13952207

申请日：2013-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Dongchan Kim ,  Gyungjin Min ,  Jaehong Park ,  Yongmoon Jang ,  Je-Woo Han

IPC: H01L21/20 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L28/90

Abstract: A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes.

Abstract translation: 制造具有电容器的半导体器件的方法可以包括在下部结构上形成模具结构，图案化模具结构以形成暴露下部结构的多个孔，在由孔露出的模具结构的侧壁上形成保护层， 在设置有保护层的孔中形成下电极，去除模具结构以露出​​保护层，去除保护层以暴露下电极的侧壁，并且在下电极上依次形成电介质膜和上电极。

公开(公告)号：US11854892B2

公开(公告)日：2023-12-26

申请号：US17699570

申请日：2022-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Jungchul Lee ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  H01L21/304

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6836 ,  H01L2221/68336

Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.

公开(公告)号：US20230395547A1

公开(公告)日：2023-12-07

申请号：US18205329

申请日：2023-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyun Kweon ,  Yeongbeom Ko ,  Wooju Kim ,  Jungseok Ryu ,  Junho Yoon ,  Hwayoung Lee

IPC: H01L23/00 ,  H10B80/00

CPC classification number: H01L24/08 ,  H10B80/00 ,  H01L2224/08145

Abstract: A semiconductor device includes a first chip structure including a wiring structure disposed on a circuit elements, and first bonding metal layers and a first bonding insulating layer on the wiring structure, an upper surface of the first chip structure having an edge region and an inner region surrounded by the edge region, a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer bonded to the first bonding insulating layer, and a memory cell layer on the second bonding metal layers and the second bonding insulating layer, an insulating capping layer disposed on an upper surface of the second chip structure and extending to the edge region, and a connection pad disposed on a region of the insulating capping layer.

公开(公告)号：US20230082384A1

公开(公告)日：2023-03-16

申请号：US17730993

申请日：2022-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Yeongbeom Ko ,  Hwayoung Lee ,  Junggeun Shin ,  Hyunsu Sim ,  Kwangyong Lee ,  Jongho Lee

IPC: H01L21/67 ,  H01L21/683 ,  B23K26/53

Abstract: A substrate processing apparatus includes a chuck table including a mounting table having a mounting surface on which a substrate is mounted, wherein the mounting surface is a curved surface; and a laser supply head configured to irradiate the substrate attached to the mounting table with a laser beam.

公开(公告)号：US20220392851A1

公开(公告)日：2022-12-08

申请号：US17674549

申请日：2022-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwayoung Lee ,  Hyunsu Sim ,  Junho Yoon

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/78

Abstract: A method of manufacturing a semiconductor chip includes preparing a semiconductor substrate having an active surface on which a device layer is provided and an inactive surface opposite to the active surface, the device layer having a integrated circuit (IC) areas and a cut area provided between adjacent IC areas; forming anti-collision recesses in regions of the cut area that are adjacent to corners of the IC areas, each of the anti-collision recesses having rounded internal sidewalls, each of the rounded internal sidewalls corresponding to a respective corner of the adjacent corners; forming a modified portion in the semiconductor substrate by irradiating a cut line of the cut area with a laser; polishing the inactive surface of the semiconductor substrate, wherein cracks propagate from the modified portion in a vertical direction of the semiconductor substrate; and separating the IC areas from each other along the cracks to form semiconductor chips.