公开(公告)号：US11521981B2

公开(公告)日：2022-12-06

申请号：US17095821

申请日：2020-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangyoung Jung ,  Sangyoun Jo ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  G11C7/18 ,  H01L27/11519 ,  G11C16/08 ,  H01L27/11534 ,  H01L27/11565

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.

公开(公告)号：US11450681B2

公开(公告)日：2022-09-20

申请号：US16844234

申请日：2020-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haemin Lee ,  Jongwon Kim ,  Shinhwan Kang ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11578

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

公开(公告)号：US20220149060A1

公开(公告)日：2022-05-12

申请号：US17362903

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAERYONG SIM ,  Giyong Chung ,  Dongsik Oh ,  Jeehoon Han

IPC: H01L27/11529 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28

Abstract: A semiconductor device includes a substrate that includes a first active region, a second active region, and an isolation region. An isolation layer pattern fills a trench in the substrate. A first gate insulation layer pattern and a first gate, electrode structure are formed on the first active region. A second gate insulation layer pattern and second gate electrode structure are formed on the second active region. The first gate electrode structure includes a first polysilicon pattern, a second polysilicon pattern, and a first metal pattern. The second gate electrode structure includes a third polysilicon pattern, a fourth polysilicon pattern, and a second metal pattern. An upper surface of the isolation layer pattern is higher than upper surfaces of each of the first and third polysilicon patterns. A sidewall of each of the first and third polysilicon patterns contacts sidewalls of the isolation layer pattern.

公开(公告)号：US11114461B2

公开(公告)日：2021-09-07

申请号：US16700059

申请日：2019-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon Ahn ,  Jaeryong Sim ,  Giyong Chung ,  Jeehoon Han

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/60 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor lavers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

公开(公告)号：US20250133739A1

公开(公告)日：2025-04-24

申请号：US19003011

申请日：2024-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Jeehoon Han

IPC: H10B43/27 ,  H10B41/20 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10D30/69 ,  H10D64/23 ,  H10K19/00

Abstract: Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.

公开(公告)号：US12131995B2

公开(公告)日：2024-10-29

申请号：US18370913

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H10B43/27 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L23/5283 ,  H01L29/42356 ,  H10B43/27

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US12114504B2

公开(公告)日：2024-10-08

申请号：US17321747

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoon Kim ,  Jaeryong Sim ,  Jeehoon Han

IPC: H10B43/50 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: An integrated circuit device includes a substrate, a peripheral circuit structure disposed on the substrate, the peripheral circuit structure including a peripheral circuit and a lower wiring connected to the peripheral circuit, a conductive plate covering a portion of the peripheral circuit structure, a cell array structure disposed on the peripheral circuit structure with the conductive plate therebetween, the cell array structure including a memory cell array and an insulation layer surrounding the memory cell array, a through hole via passing through the insulation layer in a direction vertical to a top surface of the substrate to be connected to the lower wiring, and an etch guide member disposed in the insulation layer at the same level as the conductive plate to contact a portion of the through hole via.

公开(公告)号：US20240237353A1

公开(公告)日：2024-07-11

申请号：US18613389

申请日：2024-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Jeehoon Han

IPC: H10B43/27 ,  H01L29/417 ,  H01L29/423 ,  H10B41/20 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10K19/00

CPC classification number: H10B43/27 ,  H01L29/41741 ,  H01L29/42344 ,  H10B41/20 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10K19/201

Abstract: Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.

公开(公告)号：US20230157023A1

公开(公告)日：2023-05-18

申请号：US18094007

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Son ,  Sanghoon Jeong ,  Sangjun Hong ,  Seogoo Kang ,  Jeehoon Han

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

公开(公告)号：US11616078B2

公开(公告)日：2023-03-28

申请号：US17406245

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongseon Ahn ,  Jaeryong Sim ,  Giyong Chung ,  Jeehoon Han

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/60 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor layers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.