公开(公告)号：US20210159331A1

公开(公告)日：2021-05-27

申请号：US17095241

申请日：2020-11-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Satoru TOKUDA ,  Ryuuji UMEMOTO ,  Katsumi EIKYU ,  Hiroshi YANAGIGAWA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.

公开(公告)号：US20150130009A1

公开(公告)日：2015-05-14

申请号：US14528724

申请日：2014-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Atsushi SAKAI ,  Hiroyuki ARIE

IPC: H01L27/146 ,  H01L31/18 ,  H01L31/028

CPC classification number: H01L27/14645 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1804

Abstract: To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer.

Abstract translation: 为了提供具有高灵敏度的光电转换元件的半导体器件，引起较少的起霜，并且能够提供高可靠性的图像。 半导体器件具有半导体衬底，第一p型外延层，第二p型外延层和第一光电转换元件。 第一p型外延层形成在半导体衬底的主表面上。 形成第二p型外延层以覆盖第一p型外延层的上表面。 第一光电转换元件形成在第二p型外延层中。 第一和第二p型外延层各自由硅制成，并且第一p型外延层的p型杂质浓度高于第二p型外延层的p型杂质浓度。

公开(公告)号：US20230335635A1

公开(公告)日：2023-10-19

申请号：US17722788

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Atsushi SAKAI ,  Yotaro GOTO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402

Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

公开(公告)号：US20230111142A1

公开(公告)日：2023-04-13

申请号：US17886049

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Yuta NABUCHI ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a plurality of unit cells. Each of the plurality of unit cells has a pair of column regions, a pair of trenches formed between the pair of column regions in the X direction, and a pair of gate electrodes formed in the pair of trenches via a gate insulating film, respectively. The two unit cells adjacent in the X direction share one column region of the pair of column regions and are arranged to be symmetrical about the shared column region. Here, a distance between the two trenches, which are adjacent with the one column region interposed therebetween, of the trenches in the two adjacent unit cells is different from a distance between the pair of trenches in the one unit cell.

公开(公告)号：US20190067470A1

公开(公告)日：2019-02-28

申请号：US16036489

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Hiroki FUJII ,  Atsushi SAKAI ,  Takahiro MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.

公开(公告)号：US20160163897A1

公开(公告)日：2016-06-09

申请号：US14948190

申请日：2015-11-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L31/0352 ,  H01L31/103 ,  H01L27/146

CPC classification number: H01L31/03529 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/103 ,  Y02E10/50

Abstract: To provide an imaging device equipped with a photodiode, which is capable of enhancing both of a capacity and sensitivity.In an area of a P-type well in which a photodiode is formed, a P-type impurity region is formed from the surface of the P-type well to a predetermined depth. Further, an N-type impurity region is formed to extend to a deeper position. N-type impurity regions and P-type impurity regions respectively extending in a gate width direction from a lower part of the N-type impurity region to a deeper position so as to contact the N-type impurity region are alternately arranged in a plural form along a gate length direction in a form to contact each other.

Abstract translation: 提供配备有光电二极管的成像装置，其能够增强容量和灵敏度。 在其中形成光电二极管的P型阱的区域中，从P型阱的表面到预定深度形成P型杂质区。 此外，形成N型杂质区域以延伸到更深的位置。 分别从N型杂质区域的下部向栅极宽度方向延伸以与N型杂质区域接触的较深位置的N型杂质区域和P型杂质区域以多种形式交替排列 沿着栅极长度方向以彼此接触的形式。

公开(公告)号：US20230369414A1

公开(公告)日：2023-11-16

申请号：US18358474

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/66734 ,  H01L29/7813

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20230112550A1

公开(公告)日：2023-04-13

申请号：US17886073

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Hiroshi YANAGIGAWA ,  Katsumi EIKYU ,  Atsushi SAKAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/266

Abstract: A semiconductor device and a method of manufacturing the same capable of ensuring a sufficient breakdown voltage near a terminal end portion of a cell portion are provided. The cell portion includes a first cell column region and a second cell column region adjacent to each other, and a first cell trench gate and a second cell trench gate arranged between the first cell column region and the second cell column region. An outer peripheral portion includes an outer peripheral trench gate connected to an end portion of each of the first cell trench gate and the second cell trench gate, and a first outer peripheral column region arranged on the cell portion side with respect to the outer peripheral trench gate and extended across the first cell trench gate and the second cell trench gate in plan view.

公开(公告)号：US20190237577A1

公开(公告)日：2019-08-01

申请号：US16223839

申请日：2018-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0274 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66068

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20190198663A1

公开(公告)日：2019-06-27

申请号：US16192480

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.