公开(公告)号：US20170250259A1

公开(公告)日：2017-08-31

申请号：US15411987

申请日：2017-01-21

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MORI

IPC: H01L29/40 ,  H01L29/10 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/408 ,  H01L21/26513 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.

公开(公告)号：US20180182890A1

公开(公告)日：2018-06-28

申请号：US15845628

申请日：2017-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MORI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7835

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface, an insulating isolation film disposed at the first surface, and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The insulating isolation film has a first portion disposed inside the drift region in plan view, a second portion protruding from the first portion in a direction toward the source region, and a third portion protruding from the first portion in the direction toward the source region and sandwiching the drift region between the second portion and the third portion. The gate electrode faces a portion of the body region sandwiched between the source region and the drift region with being insulated from the portion. The gate electrode is disposed so as to extend over the second portion and the third portion.

公开(公告)号：US20180145132A1

公开(公告)日：2018-05-24

申请号：US15810011

申请日：2017-11-11

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MORI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface, an insulating isolation structure having a first depth, and a gate electrode. The semiconductor substrate has source and drain regions, a reverse conductivity region having a second depth, a body region, and a drift region. The source region, the drift region, and the drain region are of a first conductivity type, and the body region and the reverse conductivity region are of a second conductivity type which is opposite to the first conductivity type. The insulating isolation structure is disposed between the drain region and the reverse conductivity region. The first depth is larger than the second depth.

公开(公告)号：US20150115410A1

公开(公告)日：2015-04-30

申请号：US14516806

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU ,  Takahiro MORI ,  Tetsuya NITTA

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L23/53223 ,  H01L23/53266 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

Abstract translation: 多个第一布线层布置在基板的主表面上，第一绝缘膜布置在多个第一布线层的上表面上，第二绝缘膜布置在第一绝缘膜的上表面上，并且 多个第二布线层布置在第二绝缘膜上。 金属电阻元件层布置在多个第二布线层中的至少一个第二布线层正下方。 多个导电层在垂直于主表面的Z方向上从多个第二布线层分别延伸到金属电阻元件层。 金属电阻元件层包括金属布线层。 多个导电层中的至少一个导电层的侧面的至少一部分连接到金属布线层。

公开(公告)号：US20240178317A1

公开(公告)日：2024-05-30

申请号：US18484956

申请日：2023-10-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MORI

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66681

Abstract: In a p-type substrate region of a semiconductor substrate, an n-type source region, an n-type drain region, a p-type body region having an impurity concentration higher than an impurity concentration of the p-type substrate region, a p-type body contact region having an impurity concentration higher than the impurity concentration of the p-type body region, and an n-type drift region having an impurity concentration lower than an impurity concentration of the n-type drain region are formed. A gate electrode is formed on the semiconductor substrate via a gate dielectric film. The semiconductor substrate includes a first region and a second region that are alternately disposed in an extending direction of the gate electrode. A width of the p-type body region overlapping with the gate electrode in the second region is smaller than a width of the p-type body region overlapping with the gate electrode in the first region.

公开(公告)号：US20190334001A1

公开(公告)日：2019-10-31

申请号：US16504969

申请日：2019-07-08

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MORI

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

Abstract: A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.

公开(公告)号：US20190326434A1

公开(公告)日：2019-10-24

申请号：US16375634

申请日：2019-04-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki SEKIKAWA ,  Takahiro MORI ,  Yuji ISHII

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L21/033 ,  H01L21/308 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device of one embodiment includes the steps of: forming a drift region in a first surface of a semiconductor substrate; forming a body region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the drift region; forming a hard mask, having an opening over the drift region, in the first surface; forming a reverse conductivity region in the first surface by ion implantation using the hard mask; forming a trench in the first surface by anisotropic etching using the hard mask; and embedding an isolation film in the trench. The ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part, which is located on a first portion side of the opening, of the hard mask.

公开(公告)号：US20190067470A1

公开(公告)日：2019-02-28

申请号：US16036489

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Hiroki FUJII ,  Atsushi SAKAI ,  Takahiro MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.

公开(公告)号：US20180175192A1

公开(公告)日：2018-06-21

申请号：US15847342

申请日：2017-12-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki FUJII ,  Takahiro MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0607 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A recessed portion is formed in a top surface of an isolation insulation film filling an isolation trench between a p+ source region and a p+ drain region. A p− drift region is located below the isolation trench and connected to the p+ drain region. A gate electrode fills the recessed portion. An n-type impurity region is located below the p− drift region and directly below the recessed portion.

公开(公告)号：US20170025532A1

公开(公告)日：2017-01-26

申请号：US15172264

申请日：2016-06-03

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MORI ,  Hiroki FUJII

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/311 ,  H01L29/0611 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor.In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

Abstract translation: 在具有横向MOS晶体管的半导体器件中，在位于漏区和栅电极之间的隔离绝缘膜的一部分处形成掩埋电极。 掩埋电极包括埋设部分。 掩埋部分由隔离绝缘膜的表面形成，直到与隔离绝缘膜的厚度相比较的深度。 掩埋电极电耦合到漏极区域。