公开(公告)号：US10224285B2

公开(公告)日：2019-03-05

申请号：US15438148

申请日：2017-02-21

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Eduardo M. Chumbes ,  Kelly P. Ip ,  Thomas E. Kazior

IPC: H01L29/20 ,  H01L29/45 ,  H01L21/324 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/417

Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

公开(公告)号：US20160211136A1

公开(公告)日：2016-07-21

申请号：US15082500

申请日：2016-03-28

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior

IPC: H01L21/02 ,  H01L21/762

CPC classification number: H01L21/0254 ,  H01L21/6835 ,  H01L21/7605 ,  H01L21/76251 ,  H01L21/76256 ,  H01L21/8258 ,  H01L23/66 ,  H01L29/2003 ,  H01L2221/68327 ,  H01L2224/32145 ,  H01L2924/0002 ,  H01P11/003 ,  H01L2924/00

Abstract: A method for providing a semi conductor structure includes: providing a structure having: layer comprising silicon, such as a layer of silicon or silicon carbide; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon; forming a Group III-V device in the III-V layer and a strip conductor connected to the device; removing silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.

Abstract translation: 一种提供半导体结构的方法包括：提供一种结构，其具有：包含硅的层，例如硅或碳化硅层; 结合结构; 和硅层，所述接合结构设置在包含硅和所述硅层的层之间，所述硅层比包含硅的层厚; 以及设置在包含硅的层的上表面上的III-V族层; 在III-V层中形成III-V族元件，连接到器件上的条形导体; 去除硅层和结合结构以暴露包含硅的层的底表面; 以及在包含硅的层的暴露的底表面上形成接地平面导体，以提供带状导体和接地平面导体的微带传输线。

公开(公告)号：US09231064B1

公开(公告)日：2016-01-05

申请号：US14457436

申请日：2014-08-12

Applicant: Raytheon Company

Inventor： Shahed Reza ,  Eduardo M. Chumbes ,  Thomas E. Kazior ,  Gerhard Sollner

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/335 ,  H01L29/36 ,  H01L29/205 ,  H01L29/20 ,  H01L21/265

CPC classification number: H01L29/36 ,  H01L21/2654 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/66462 ,  H01L29/7784 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7789

Abstract: A semiconductor structure having: a Group III-N channel layer, a Group III-N top-barrier polarization-generating layer forming a heterojunction with an upper surface of the channel layer; and a Group III-N back-barrier polarization-generating layer forming a heterojunction with a lower surface of the channel layer. The channel layer has disposed therein a predetermined n-type conductive dopant.

Abstract translation: 一种半导体结构，其具有：III-N族沟道层，与所述沟道层的上表面形成异质结的III-N族顶部势垒极化发生层; 以及与沟道层的下表面形成异质结的III-N族背向阻挡极化发生层。 沟道层在其中设置有预定的n型导电掺杂剂。

公开(公告)号：US11515410B2

公开(公告)日：2022-11-29

申请号：US17085171

申请日：2020-10-30

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior ,  Eduardo M. Chumbes

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/08 ,  H01L29/20 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

公开(公告)号：US11239326B2

公开(公告)日：2022-02-01

申请号：US16381485

申请日：2019-04-11

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior ,  Kamal Tabatabaie Alavi

IPC: H01L29/40 ,  H01L21/285 ,  H01L23/48 ,  H01L23/485 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L23/535 ,  H01L21/28 ,  H01L29/423 ,  H01L23/532 ,  H01L29/51

Abstract: A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.

公开(公告)号：US11177216B2

公开(公告)日：2021-11-16

申请号：US16123429

申请日：2018-09-06

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Eduardo M. Chumbes ,  Kelly P. Ip ,  Thomas E. Kazior

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L29/20 ,  H01L29/778

Abstract: A semiconductor structure having: a Group III-N semiconductor; a first dielectric disposed in direct contact with the Group III-N semiconductor; a second dielectric disposed over the first dielectric, the first dielectric having a higher dielectric constant than the second dielectric; a third dielectric layer disposed on the first dielectric layer, such third dielectric layer having sidewall abutting sides of the second dielectric layer; and a gate electrode contact structure. The gate electrode structure comprises: stem portion passing through, and in contact with, the first dielectric and the second dielectric having bottom in contact with the Group III-V semiconductor; and, an upper, horizontal portion extending beyond the stem portion and abutting sides of the third dielectric layer. An electrical interconnect structure has side portions passing through and in contact with the third dielectric layer and has a bottom portion in contact with the horizontal portion of the gate electrode contact structure.

公开(公告)号：US10930742B2

公开(公告)日：2021-02-23

申请号：US16821559

申请日：2020-03-17

Applicant: RAYTHEON COMPANY

Inventor： Hooman Kazemi ,  Mark Rosker ,  Thomas E. Kazior ,  Shane A. O'Connor ,  Emily Elswick

IPC: H01L23/482 ,  H01L23/552 ,  H01L23/538 ,  H01L29/20 ,  H01L23/29

Abstract: A reconstituted wafer includes a plurality of apertures defined in a first substrate. A module is positioned in each aperture and coupled to circuit traces on the first substrate by operation of beam leads extending from the module. A second substrate is positioned over the first substrate and each module is enclosed in a space defined by the respective aperture and the second substrate. The module includes a lid and at least one mode suppression circuit disposed in the lid. The modules may include an invariant die where different technologies are stacked together.

公开(公告)号：US20220140126A1

公开(公告)日：2022-05-05

申请号：US17085171

申请日：2020-10-30

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior ,  Eduardo M. Chumbes

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/66 ,  H01L29/04 ,  H01L29/45 ,  H01L29/423

Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

公开(公告)号：US20210249331A1

公开(公告)日：2021-08-12

申请号：US17169914

申请日：2021-02-08

Applicant: The Regents of the University of California ,  The Board of Trustees of the Leland Stanford Junior University ,  Raytheon Company

Inventor： Scott Ueda ,  Aaron McLeod ,  Andrew Kummel ,  Mike Burkland ,  Eduardo M. Chumbes ,  Thomas E. Kazior ,  Eric Pop ,  Michelle Chen ,  Chris Perez ,  Mark Rodwell

IPC: H01L23/373 ,  H01L21/48

Abstract: Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.

公开(公告)号：US20190097001A1

公开(公告)日：2019-03-28

申请号：US15714382

申请日：2017-09-25

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior ,  Kamal Tabatabaie Alavi

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L23/535

Abstract: A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.