公开(公告)号：US20170249149A1

公开(公告)日：2017-08-31

申请号：US15057116

申请日：2016-02-29

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Rami Mohammad AL SHEIKH ,  Raguram DAMODARAN ,  Michael Scott MCILVAINE ,  Jeffrey Todd BRIDGES

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30083 ,  G06F9/30021 ,  G06F9/30058 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3867

Abstract: Systems and methods for operating a processor include determining confidence levels, such as high, low, and medium confidence levels, associated with in-flight branch instructions in an instruction pipeline of the processor, based on counters used for predicting directions of the in-flight branch instructions. Numbers of in-flight branch instructions associated with each of confidence levels are determined. A weighted sum of the numbers weighted with weights corresponding to the confidence levels is calculated and the weighted sum is compared with a threshold. A throttling signal may be asserted to indicate that instructions are to be throttled in a pipeline stage of the instruction pipeline based on the comparison.

公开(公告)号：US20170090508A1

公开(公告)日：2017-03-30

申请号：US14865092

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Anil KRISHNA ,  Raguram DAMODARAN ,  Jeffrey Todd BRIDGES ,  Thomas Philip SPEIER ,  Rodney Wayne SMITH ,  Keith Alan BOWMAN ,  David Joseph Winston HANSQUINE

IPC: G06F1/08 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/60 ,  Y02D10/126 ,  Y02D10/152

Abstract: The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

公开(公告)号：US20190087192A1

公开(公告)日：2019-03-21

申请号：US15712119

申请日：2017-09-21

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Rami Mohammad A. AL SHEIKH ,  Brandon DWIEL ,  Derek HOWER

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/325 ,  G06F9/3808 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/3867

Abstract: Systems and methods for constructing an instruction slice for prefetching data of a data-dependent load instruction include a slicer for identifying a load instruction in an instruction sequence as a first occurrence of a qualified load instruction which will miss in a last-level cache. A commit buffer stores information pertaining to the first occurrence of the qualified load instruction and shadow instructions which follow. For a second occurrence of the qualified load instruction, an instruction slice is constructed from the information in the commit buffer to form a slice payload. A pre-execution engine pre-executes the instruction slice based on the slice payload to determine an address from which data is to be fetched for execution of a third and any subsequent occurrences of the qualified load instruction. The data is prefetched from the determined address for the third and any subsequent occurrence of the qualified load instruction.

公开(公告)号：US20170090936A1

公开(公告)日：2017-03-30

申请号：US15087728

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Rami Mohammad AL SHEIKH ,  Shivam PRIYADARSHI

IPC: G06F9/38 ,  G06N7/00 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/30145 ,  G06F9/3806 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3844 ,  G06N7/005

Abstract: A method for instruction signature based (ISB) speculative optimization includes storing a plurality of entries. Each entry of the plurality of entries includes an instruction signature tag and an ISB predictor effectiveness measurement. The instruction signature tag corresponds to an instruction signature and the ISB predictor effectiveness measurement is based, least in part, on an effectiveness of a predictor when applied to the instruction signature. The method also includes detecting a to-be-executed instruction signature and determining if the plurality of entries includes a matching entry. The matching entry has an instruction signature tag corresponding to the to-be-executed instruction signature. Upon determining that the plurality of entries includes the matching entry, the method includes controlling an application of the predictor to the to-be-executed instruction signature, based at least in part on the ISB predictor effectiveness measurement in the matching entry.

公开(公告)号：US20170046159A1

公开(公告)日：2017-02-16

申请号：US14827262

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Rami Mohammad AL SHEIKH ,  Raguram DAMODARAN

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3804 ,  G06F9/3802 ,  G06F9/3844 ,  G06F12/0875 ,  G06F2212/452

Abstract: Systems and methods relate to an instruction fetch unit of a processor, such as a superscalar processor. The instruction fetch unit includes a fetch bandwidth predictor (FBWP) configured to predict a number of instructions to be fetched in a fetch group of instructions in a pipeline stage of the processor. A first entry of the FBWP corresponding to the fetch group corresponds to a prediction of the number of instructions to be fetched, based on occurrence and location of a predicted taken branch instruction in the fetch group and a confidence level associated with the predicted number in the prediction field. The instruction fetch unit is configured to fetch only the predicted number of instructions, rather than the maximum number of entries that can be fetched in the pipeline stage, if the confidence level is greater than a predetermined threshold. In this manner, wasteful fetching of instructions is avoided.

Abstract translation: 系统和方法涉及诸如超标量处理器的处理器的指令提取单元。 指令提取单元包括获取带宽预测器（FBWP），其被配置为预测将在处理器的流水线级中的取指令组中提取的指令数量。 对应于取出组的FBWP的第一条目对应于基于取出组中预测的分支指令的出现和位置以及与所提取的预测数相关联的置信水平的待提取的指令数量的预测 预测领域。 如果置信水平大于预定阈值，则指令提取单元被配置为仅获取预测数量的指令，而不是在流水线级中可以获取的最大条目数。 以这种方式，避免了浪费的指令提取。