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公开(公告)号：US10665370B2
公开(公告)日：2020-05-26
申请号：US16058928
申请日：2018-08-08
Applicant: QUALCOMM Incorporated
Inventor： Haitao Cheng , Chao Song , Ye Lu
Abstract: A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.
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公开(公告)号：US10651268B2
公开(公告)日：2020-05-12
申请号：US16009976
申请日：2018-06-15
Applicant: QUALCOMM Incorporated
Inventor： Haitao Cheng , Ye Lu , Chao Song
Abstract: A capacitor has reduced misalignment in the interconnect layers and lower capacitance variance. The capacitor includes a first endcap having a first section and a second section orthogonal to the first section. The capacitor includes a first set of conductive fingers orthogonally coupled to the first section. The capacitor includes a third set of conductive fingers orthogonally coupled to the second section of the endcap and a second endcap parallel to the first section of the endcap. The capacitor includes a second set of conductive fingers orthogonally coupled to a second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.
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Patent Agency Ranking
公开(公告)号：US10600731B2
公开(公告)日：2020-03-24
申请号：US16006657
申请日：2018-06-12
Applicant: QUALCOMM Incorporated
Inventor： Haitao Cheng , Zhang Jin
IPC: H01L27/08 , H01L23/522 , H01L23/528 , H01L49/02 , H03H1/00
Abstract: An integrated circuit includes a capacitor (e.g., a folded metal-oxide-metal (MOM) capacitor) formed in the lower BEOL interconnect levels, without degrading an inductor's Q-factor. The integrated circuit includes the capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The integrated circuit also includes an inductive trace having one or more turns in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor.
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公开(公告)号：US11302773B2
公开(公告)日：2022-04-12
申请号：US16155694
申请日：2018-10-09
Applicant: QUALCOMM Incorporated
Inventor： Ye Lu , Junjing Bao , Haitao Cheng , Chao Song
IPC: H01L49/02 , H01L23/522 , H01L23/532
Abstract: A low cost capacitor (e.g., metal-insulator-metal (MIM) capacitor) is included in the back-end-of-line layers for effective routing and area savings. The capacitor has a first electrode (e.g., a first terminal of the capacitor) including a conductive back-end-of-line (BEOL) layer and a second electrode (e.g., a second terminal of the capacitor) including a nitride-based metal. The capacitor also has an etch stop layer (e.g., a dielectric of the capacitor) between the first electrode and the second electrode.
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公开(公告)号：US20190326057A1
公开(公告)日：2019-10-24
申请号：US15961594
申请日：2018-04-24
Applicant: QUALCOMM Incorporated
Inventor： Ye Lu , Haitao Cheng , Chao Song
IPC: H01G4/10 , H01G4/01 , H01L23/522
Abstract: Methods, systems, and devices for a finger metal-on-metal (FMOM) capacitor including a negative capacitance material are described. In one examples, a FMOM capacitor may include a first electrode and a second electrode. The FMOM capacitor may include a dielectric layer coating a first sidewall of the first electrode and a second sidewall of a second electrode. A portion of the first sidewall may be substantially parallel to a portion of the second sidewall. The FMOM capacitor may also include a negative capacitance material disposed in a channel between the first sidewall of the first electrode and the second sidewall of the second electrode. The negative capacitance material may extend in a direction that is substantially parallel to the portion of the first sidewall and the portion of the second sidewall.
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公开(公告)号：US10431540B1
公开(公告)日：2019-10-01
申请号：US16039213
申请日：2018-07-18
Applicant: QUALCOMM Incorporated
Inventor： Haitao Cheng , Chao Song , Ye Lu
IPC: H01L21/02 , H01L23/522 , H03F3/195 , H01L49/02 , H01L23/66
Abstract: A semiconductor device reduces parasitic capacitance between a metal-oxide-metal (MOM)/metal-insulator-metal (MIM) capacitors and a semiconductor substrate. The semiconductor device includes the semiconductor substrate (e.g., a silicon substrate, a III-V compound semiconductor substrate, or a silicon on insulator (SOI) substrate), a magnetic material layer, and a capacitor. The magnetic material layer is between the semiconductor substrate and the capacitor.
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公开(公告)号：US10312891B1
公开(公告)日：2019-06-04
申请号：US16142476
申请日：2018-09-26
Applicant: QUALCOMM Incorporated
Inventor： Chao Song , Zhengzheng Wu , Haitao Cheng , Ye Lu
Abstract: In certain aspects, an integrated circuit comprises a signal path having a path delay from an input to an output, wherein the signal path comprises a path capacitor having a path capacitance. The integrated circuit also comprises a variation tracking circuit coupled to the signal path, wherein the variation tracking circuit comprises a tracking resistor have a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation.
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