公开(公告)号：US09625924B2

公开(公告)日：2017-04-18

申请号：US14860717

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Hoan Huu Nguyen ,  Keith Alan Bowman ,  Yeshwant Nagaraj Kolla ,  Burt Lee Price ,  Samantak Gangopadhyay

IPC: G05F1/56

CPC classification number: G05F1/56 ,  H03K19/0008

Abstract: Systems and methods relate to a low-dropout voltage (LDO) voltage regulator which receives a maximum supply voltage and provides a regulated voltage to a load, where the load may be a processing core of a multi-core processing system. A leakage current supply source includes a leakage current sensor to determine a leakage current demand of the load of the LDO voltage regulator and a leakage current supply circuit to supply the leakage current demand. In this manner, the leakage current supply source provides current assistance to the LDO voltage regulator, such that the LDO voltage regulator can supply only dynamic current. Thus, headroom voltage of the LDO voltage regulator, which is a difference between the maximum supply voltage and the regulated voltage, can be reduced. Reducing the headroom voltage allows greater number of dynamic voltage and frequency scaling states of the load.

公开(公告)号：US10424392B2

公开(公告)日：2019-09-24

申请号：US16165549

申请日：2018-10-19

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C29/52 ,  G11C11/419 ,  G11C11/00 ,  G11C11/412 ,  G11C11/418 ,  H01L27/11

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

公开(公告)号：US09940992B2

公开(公告)日：2018-04-10

申请号：US15085187

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Hoan Huu Nguyen ,  Keith Alan Bowman

IPC: G11C8/08 ,  G11C11/419 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10 ,  G11C7/06

CPC classification number: G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell is disclosed. In one aspect, a leakage-aware activation control circuit is provided for a dynamic read circuit configured to perform read operations on a memory bit cell. To prevent or mitigate contention between the delayed keeper circuit and a read port circuit in the dynamic read circuit pulling a dynamic node to opposite voltage levels when a read operation is initiated, the leakage-aware activation control circuit is configured to adaptively control activation timing of the delayed keeper circuit based on a comparison of N-type Field-Effect Transistor (NFET) leakage current to P-type FET (PFET) leakage current. In this manner, the leakage-aware activation control circuit can adaptively adjust the activation timing of the delayed keeper circuit based on the actual relative strengths of NFETs and PFETs.

公开(公告)号：US09627064B2

公开(公告)日：2017-04-18

申请号：US14860844

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Keith Alan Bowman ,  Francois Ibrahim Atallah ,  David Joseph Winston Hansquine ,  Jihoon Jeong ,  Hoan Huu Nguyen

IPC: G11C15/04 ,  H03K19/094 ,  H03K19/003 ,  G11C11/40

Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

公开(公告)号：US20160267214A1

公开(公告)日：2016-09-15

申请号：US14643096

申请日：2015-03-10

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Francois Ibrahim Atallah ,  Rashid Ahmed Akbar Attar ,  Keith Alan Bowman ,  Yang Du ,  Juzer Zainuddin Fatehi ,  Jai Ganesh Kumar ,  Yu Pu ,  Giby Samson ,  Kendrick Hoy Leong Yuen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/62 ,  G06F2217/84

Abstract: Clock tree design methods for ultra-wide voltage range circuits are disclosed. In one aspect, place and route software creates an integrated circuit (IC) in an optimal configuration at a first voltage condition. A first clock tree is created as part of the place and route process. Clock skew for the first clock tree is evaluated and minimized through insertion of bypassable delay elements. The delay elements are then removed from the wiring routing diagram. A second voltage condition is identified, and clock tree generation software is allowed to optimize the wiring routing diagram for the second voltage condition. The second clock tree generation software may insert more bypassable delay elements into the wiring routing diagram that allow clock skew optimization at the second voltage condition. The initial bypassable delay elements are then reinserted into the wiring routing diagram and a finished IC is established.

Abstract translation: 公开了用于超宽电压范围电路的时钟树设计方法。 在一个方面，放置和路由软件在第一电压条件下以最佳配置创建集成电路（IC）。 第一个时钟树是作为地点和路由过程的一部分而创建的。 通过插入可旁路延迟元件来评估和最小化第一个时钟树的时钟偏移。 然后将延迟元件从布线图中删除。 识别出第二电压条件，并允许时钟树生成软件优化第二电压条件的布线布线图。 第二个时钟树生成软件可以在布线布线图中插入更多的可旁路延迟元件，允许在第二电压条件下进行时钟偏移优化。 然后将初始可旁路延迟元件重新插入到布线布线图中，并建立成品IC。

公开(公告)号：US09429982B2

公开(公告)日：2016-08-30

申请号：US14499152

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  David Joseph Winston Hansquine ,  Richard Duane Tax ,  Robert Simpson Taylor

IPC: G06F1/04 ,  G06F1/10 ,  H03K3/012 ,  G06F1/32 ,  H03K19/00

CPC classification number: G06F1/10 ,  G06F1/32 ,  G06F1/3237 ,  H03K3/012 ,  H03K19/0008 ,  H03K19/0019 ,  Y02D10/128

Abstract: Systems and methods are directed to a configurable last level driver coupled to a inductor-capacitor (LC) tank or resonant clock, for improving energy efficiency of the resonant clock. In a warm up stage, the last level clock driver can be enabled to store energy in the LC tank, and in a gating stage, the last level clock driver can be fully or partially disabled such that energy stored in the LC tank can be recirculated into a clock distribution network. In a refreshing stage, the last level clock driver can be enabled to replenish the energy lost by the LC tank in the recirculation of energy into the clock distribution network during the gating stage. Programmable counters can be used to control durations of the warm up, gating, and refreshing stages.

Abstract translation: 系统和方法涉及耦合到电感器 - 电容器（LC）箱或谐振时钟的可配置的最后级别驱动器，用于提高谐振时钟的能量效率。 在预热阶段，最后一级时钟驱动器可以使能在LC箱中存储能量，并且在选通阶段，最后一级时钟驱动器可以被完全或部分禁用，使得储存在LC箱中的能量可以再循环 进入时钟分配网络。 在更新阶段，可以启用最后一级时钟驱动器，以便在门控阶段期间将能量损失的能量补充到能量进入时钟分配网络中。 可编程计数器可用于控制预热，门控和刷新阶段的持续时间。

公开(公告)号：US20160247557A1

公开(公告)日：2016-08-25

申请号：US14862579

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

IPC: G11C11/419

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C11/413 ,  G11C11/419 ,  G11C15/04

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of positive bitline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

Abstract translation: 公开了采用P型场效应晶体管（PFET）写入端口的存储器位单元（“位单元”）的写辅助电路。 还公开了相关方法和系统。 已经观察到，随着节点技术的尺寸缩小，PFET驱动电流（即，驱动强度）超过用于等尺寸FET的N型场效应晶体管（NFET）驱动电流。 在这方面，在一个方面，期望提供与NFET写入端口相反的具有PFET写入端口的位单元，以减少对位单元的存储器写入时间，从而提高存储器性能。 为了减轻在将数据写入位单元时可能发生的写入争用，可以采用以正位线升压电路的形式提供的写辅助电路来加强具有PFET写端口的存储器位单元中的PFET存取晶体管 s）。

公开(公告)号：US20160247556A1

公开(公告)日：2016-08-25

申请号：US14862555

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Jihoon Jeong ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Hoan Huu Nguyen

IPC: G11C11/419

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C11/413 ,  G11C11/419 ,  G11C15/04

Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

Abstract translation: 公开了采用P型场效应晶体管（PFET）写入端口的存储器位单元（“位单元”）的写辅助电路。 还公开了相关方法和系统。 已经观察到，随着节点技术的尺寸缩小，PFET驱动电流（即，驱动强度）超过用于等尺寸FET的N型场效应晶体管（NFET）驱动电流。 在这方面，在一个方面，期望提供与NFET写入端口相反的具有PFET写入端口的位单元，以减少对位单元的存储器写入时间，从而提高存储器性能。 为了减轻在将数据写入位单元时可能发生的写入争用，可以采用以负字线升压电路的形式提供的写辅助电路来加强具有PFET写端口的存储器位单元中的PFET存取晶体管 s）。

公开(公告)号：US20160247555A1

公开(公告)日：2016-08-25

申请号：US14862483

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Hoann Huu Nguyen ,  Francois Ibrahim Atallah ,  Keith Alan Bowman ,  David Joseph Winston Hansquine ,  Jihoon Jeong

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/065 ,  G11C7/08 ,  G11C11/412 ,  G11C11/418

Abstract: P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells (“bit cells”) are disclosed. Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sense bit line voltage(s) of the bit cells for reading the data stored in the bit cells. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-effect Transistor (NFET) drive current due for like-dimensioned FETs. In this regard, in one aspect, PFET-based sense amplifiers are provided in a memory system to increase memory read times to the bit cells, and thus improve memory read performance.

Abstract translation: 公开了用于读取PFET通道存储器位单元（“位单元”）的P型场效应晶体管（PFET）读出放大器。 还公开了相关方法和系统。 感测放大器设置在存储器系统中以感测比特单元的位线电压，用于读取存储在位单元中的数据。 已经观察到，随着节点技术的尺寸缩小，PFET驱动电流（即，驱动强度）超过由类型尺寸的FET引起的N型场效应晶体管（NFET）驱动电流。 在这方面，在一方面，在存储器系统中提供基于PFET的读出放大器，以将存储器读取时间增加到位单元，从而提高存储器读取性能。

公开(公告)号：US09251875B1

公开(公告)日：2016-02-02

申请号：US14499052

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim Atallah ,  Jihoon Jeong ,  Keith Alan Bowman ,  Amey Sudhir Kulkarni ,  Jason Philip Martzloff ,  Joshua Lance Puckett

IPC: G11C7/22 ,  G11C7/12 ,  G11C5/06

CPC classification number: G11C7/12 ,  G11C5/06 ,  G11C5/147 ,  G11C7/22 ,  G11C11/419 ,  G11C2207/007

Abstract: A register file circuit according to some examples of the disclosure may include a memory cell, a header transistor circuit, and a driver circuit. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cell with the gate of the PFET header for the row being written being controlled with a pulse write signal from the driver circuit. In some examples of the disclosure, the header transistor circuit may include an NFET pull-down inserted between a virtual-vdd and ground to discharge the virtual-vdd node reducing the contention during a write operation and a clamping NFET in parallel with the PFET header to clamp the virtual-vdd node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual-vdd node from discharging all the way to ground.

Abstract translation: 根据本公开的一些示例的寄存器文件电路可以包括存储器单元，标头晶体管电路和驱动器电路。 标头晶体管电路可以包括与存储单元的PFET串联的一个或多个PFET头，用于被写入的行的PFET头的栅极被来自驱动器电路的脉冲写入信号控制。 在本公开的一些示例中，标题晶体管电路可以包括插入在虚拟vdd和地之间的NFET下拉以放电虚拟vdd节点，以减少在写入操作期间的争用，并且与PFET头并联的钳位NFET 将虚拟vdd节点钳位到略低于存储单元中的上拉PFET的阈值电压，以确保上拉PFET几乎不会关闭，并防止虚拟vdd节点一直向地面放电。