公开(公告)号：US20160239441A1

公开(公告)日：2016-08-18

申请号：US14621929

申请日：2015-02-13

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI

IPC: G06F13/26 ,  G06F13/18

CPC classification number: G06F13/26 ,  G06F9/4818 ,  G06F13/18

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing an interrupt signal to a processing unit; determining a priority for the maintenance event; and scheduling the maintenance event according to the priority.

Abstract translation: 公开了用于调度易失性存储器维护事件的系统，方法和计算机程序。 一个实施例是一种方法，包括：存储器控制器，其确定用于经由存储器数据接口耦合到存储器控制器的易失性存储器设备执行维护事件的服务时间（ToS）窗口; 所述存储器控制器向处理单元提供中断信号; 确定维护事件的优先级; 并根据优先级调度维护事件。

公开(公告)号：US20150243373A1

公开(公告)日：2015-08-27

申请号：US14187279

申请日：2014-02-23

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  XIANGYU DONG ,  JUNGWON SUH ,  JUNG PILL KIM ,  DEEPTI VIJAYALAKSHMI SRIRAMAGIRI

IPC: G11C29/44 ,  G06F11/20 ,  G06F11/10

CPC classification number: G11C29/44 ,  G06F11/1048 ,  G06F11/1076 ,  G06F11/2053 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C2029/4402

Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

Abstract translation: 公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。 一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关联的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误数量超过错误计数阈值，则退出对应于物理地址的内核页面。

公开(公告)号：US20150242213A1

公开(公告)日：2015-08-27

申请号：US14187272

申请日：2014-02-23

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  DEXTER TAMIO CHUN ,  DHAMIM PACKER ALI ,  GREGORY AMERIADA UVIEGHARA ,  ZHONGZE WANG

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F8/66 ,  G06F12/0638

Abstract: Various embodiments of methods and systems for flexible read only memory (“ROM”) storage of coded instructions in a portable computing device (“PCD”) are disclosed. Because certain instructions and/or data associated with a primary boot loader (“PBL”) may be defective or in need of modification after manufacture of a mask ROM component, embodiments of flexible ROM storage (“FRS”) systems and methods use a closely coupled one-time programmable (“OTP”) memory component to store modified instructions and/or data. Advantageously, because the OTP memory component may be manufactured “blank” and programmed at a later time, modifications to code and/or data stored in an unchangeable mask ROM may be accomplished via pointers in fuses of a security controller that branch the request to the OTP and bypass the mask ROM.

Abstract translation: 公开了用于便携式计算设备（“PCD”）中的编码指令的灵活的只读存储器（“ROM”）存储的方法和系统的各种实施例。 由于与主引导加载程序（“PBL”）相关联的某些指令和/或数据在制造掩模ROM组件之后可能是有缺陷的或需要修改的，所以灵活的ROM存储（“FRS”）系统和方法的实施例使用紧密的 耦合的一次性可编程（“OTP”）存储器组件来存储经修改的指令和/或数据。 有利地，因为OTP存储器组件可以在稍后的时间被制造为“空白”并被编程，所以可以通过安全控制器的熔丝中的指针来实现对不可改变的掩模ROM中存储的代码和/或数据的修改，该安全控制器的熔丝将该请求分配到 OTP并绕过掩模ROM。

公开(公告)号：US20190065087A1

公开(公告)日：2019-02-28

申请号：US15684838

申请日：2017-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  Larry Bassel ,  Thomas Zeng ,  Dexter Chun

IPC: G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for reducing memory power consumption. An exemplary method comprises configuring a power saving memory balloon associated with a volatile memory. Memory allocations are steered to the power saving memory balloon. In response to initiating a memory power saving mode, data is migrated from the power saving memory balloon. A power saving feature is executed on the power saving memory balloon while in the memory power saving mode.

公开(公告)号：US20170277460A1

公开(公告)日：2017-09-28

申请号：US15081914

申请日：2016-03-27

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  DEXTER TAMIO CHUN ,  ALAIN ARTIERI

IPC: G06F3/06 ,  G11C11/406 ,  G11C7/10 ,  G06F12/08

CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3275 ,  G06F12/0862 ,  G06F13/1689 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/602 ,  G11C11/40607 ,  G11C2211/4067 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

公开(公告)号：US20170109090A1

公开(公告)日：2017-04-20

申请号：US14885797

申请日：2015-10-16

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  ALEXANDER GANTMAN

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/06

CPC classification number: G06F3/0625 ,  G06F3/064 ,  G06F3/0673 ,  G06F12/0292 ,  G06F12/0607 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/20 ,  G06F2212/65 ,  Y02D10/13

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method comprises configuring a memory address map for two or more memory devices accessed via two or more respective memory channels. The memory address map comprises one or more interleaved blocks and a plurality of linear blocks. Each interleaved block comprises an interleaved address space for relatively higher performance tasks, and each linear block comprises a linear address space for relatively lower power tasks. A request is received from a process for a virtual memory page. The request comprises a preference for power savings or performance. If the preference is for power savings, the virtual memory page is mapped to a physical page in a concatenated linear block.

公开(公告)号：US20160320994A1

公开(公告)日：2016-11-03

申请号：US14699431

申请日：2015-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI

IPC: G06F3/06 ,  G06F9/44

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/068 ,  G06F9/4403 ,  G06F12/0238 ,  G06F12/0638 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/7204 ,  Y02D10/13

Abstract: Systems, methods, and computer programs are disclosed for providing a heterogeneous system memory in a portable communication device. One system comprises a system on chip (SoC) coupled to a nonvolatile random access memory (NVRAM) and a volatile random access memory (VRAM). The SoC comprises an operating system for mapping a heterogeneous system memory comprising the NVRAM and the VRAM. The operating system comprises a memory manager configured to allocate a first portion of the NVRAM as a block device for a swap operation, a second portion of the NVRAM for program code and read-only data, and a third portion of the NVRAM for operating system page tables. The VRAM is allocated for a program heap and a program stack.

Abstract translation: 公开了用于在便携通信设备中提供异构系统存储器的系统，方法和计算机程序。 一个系统包括耦合到非易失性随机存取存储器（NVRAM）和易失性随机存取存储器（VRAM）的片上系统（SoC）。 SoC包括用于映射包括NVRAM和VRAM的异构系统存储器的操作系统。 操作系统包括存储器管理器，其被配置为将NVRAM的第一部分分配为用于交换操作的块设备，用于程序代码和只读数据的NVRAM的第二部分以及用于操作系统的NVRAM的第三部分 页表。 VRAM被分配给程序堆和程序堆栈。

公开(公告)号：US20150293822A1

公开(公告)日：2015-10-15

申请号：US14253770

申请日：2014-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  JUNG PILL KIM ,  DEEPTI VIJAYALAKSHMI SRIRAMAGIRI

IPC: G06F11/20 ,  G06F11/14

CPC classification number: G06F11/2017 ,  G06F3/0688 ,  G06F11/0772 ,  G06F11/08 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1417 ,  G06F2201/85 ,  G06F2212/1032 ,  G06F2212/7201 ,  G11C29/00 ,  G11C29/08 ,  G11C29/52 ,  G11C29/70

Abstract: Systems, methods, and computer programs are disclosed for recovering from dynamic random access memory (DRAM) defects. One method comprises determining that an uncorrected bit error has occurred for a physical codeword address associated with a dynamic random access memory (DRAM) device coupled to a system on chip (SoC). A kernel page associated with a DRAM page comprising the physical codeword address is identified as a bad page. Recovery from the uncorrected bit error is provided by rebooting a system comprising the SoC and the DRAM device. In response to the rebooting, the identified kernel page is excluded from being allocated for DRAM operation.

Abstract translation: 公开了用于从动态随机存取存储器（DRAM）缺陷中恢复的系统，方法和计算机程序。 一种方法包括确定与耦合到片上系统（SoC）的动态随机存取存储器（DRAM）设备相关联的物理码字地址已经发生未校正的位错误。 与包括物理码字地址的DRAM页面相关联的内核页面被识别为坏页面。 通过重新启动包括SoC和DRAM设备的系统来提供从未校正的位错误的恢复。 响应于重新启动，识别的内核页面被排除在为DRAM操作分配之前。

公开(公告)号：US20190129493A1

公开(公告)日：2019-05-02

申请号：US15798116

申请日：2017-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  Azzedine Touzni ,  Dexter Tamio Chun

IPC: G06F1/32 ,  G06F9/44 ,  G06F15/78

Abstract: Systems and methods are disclosed for managing memory access for low-power use cases of a system on chip. One such method comprises booting a system on chip (SoC) comprising a plurality of SoC processing devices. A trusted channel is created to a secure non-volatile random access memory (NVRAM). The method determines a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices. A software image associated with the power-saving software program is loaded to the secure NVRAM. In response to loading the software image to the secure NVRAM, each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM are powered down.

公开(公告)号：US20180365425A1

公开(公告)日：2018-12-20

申请号：US15624612

申请日：2017-06-15

Applicant: QUALCOMM INCORPORATED

Inventor： DHAMIM PACKER ALI ,  JEFFREY SHABEL ,  YANRU LI ,  ASHUTOSH SHRIVASTAVA

IPC: G06F21/57 ,  G06F9/44

Abstract: Systems, methods, and computer programs are disclosed for securely booting a system on chip. One embodiment is a system comprising a system on chip (SoC) and a virtual collated internal memory pool (VCIMP). The SoC comprises a bootable processing device having a first internal memory, a read only memory (ROM), and one or more bootable processing subsystems each having a dedicated internal memory. The bootable processing device is configured to execute a bootloader in the ROM. The VCIMP provides time-shared control and access to the one or more bootable processing subsystems during execution of a boot sequence. The VCIMP comprises a contiguous logical-to-physical address mapping of the first internal memory residing on the bootable processing device and the dedicated internal memories residing on the corresponding one or more bootable processing subsystems.