公开(公告)号：US20180259581A1

公开(公告)日：2018-09-13

申请号：US15455253

申请日：2017-03-10

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen ,  Wah Nam Hsu ,  Yang Du

IPC: G01R31/3185 ,  H01L21/66 ,  H01L27/06 ,  H01L23/528 ,  H01L23/34 ,  H03K3/03 ,  H03K17/14

CPC classification number: G01R31/318513 ,  G01R31/318505 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5286 ,  H01L25/0657 ,  H01L27/0688 ,  H03K3/0315 ,  H03K17/14

Abstract: Dynamically controlling voltage provided to three-dimensional (3D) integrated circuits (ICs) (3DICs) to account for process variations measured across interconnected IC tiers of 3DICs are disclosed herein. In one aspect, a 3DIC process variation measurement circuit (PVMC) is provided to measure process variation. The 3DIC PVMC includes stacked logic PVMCs configured to measure process variations of devices across multiple IC tiers and process variations of vias that interconnect multiple IC tiers. The 3DIC PVMC may include IC tier logic PVMCs configured to measure process variations of devices on corresponding IC tiers. These measured process variations can be used to dynamically control supply voltage provided to the 3DIC such that operation of the 3DIC approaches a desired process corner. Adjusting supply voltage using the 3DIC PVMC takes into account interconnected properties of the 3DIC such that the supply voltage is adjusted to cause the 3DIC to operate in the desired process corner.

公开(公告)号：US09548445B2

公开(公告)日：2017-01-17

申请号：US14940996

申请日：2015-11-13

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Wei-Chuan Chen ,  Seung Kang

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  G11C11/15 ,  G11C11/16

CPC classification number: H01L43/10 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers. An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR. The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization.

Abstract translation: 垂直磁隧道结（MTJ）装置包括沉积在隧道势垒层和参考层之间的隧道磁阻（TMR）增强缓冲层。 在TMR增强缓冲层和参考层之间沉积非晶合金间隔物以增强TMR。 非晶合金间隔物阻挡面心立方（fcc）取向钉扎层的模板效应，并且在钉扎层和TMR增强缓冲层之间提供强耦合，以确保完全垂直磁化。

公开(公告)号：US09343659B1

公开(公告)日：2016-05-17

申请号：US14625494

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) device includes a top electrode or top contact above a metal hard mask which has a limited height due to process limitations in advanced nodes. The metal hard mask is provided on a magnetic tunnel junction (MTJ). The top contact for the MTJ is formed within a dielectric layer, such as a low dielectric constant (low-k) or extremely low-k layer. An additional dielectric layer is provided above the top contact for additional connections for additional circuitry to form a three-dimensional integrated circuit (3D IC).

Abstract translation: 磁阻随机存取存储器（MRAM）装置包括金属硬掩模上方的顶部电极或顶部触点，由于先进节点中的工艺限制，其具有有限的高度。 金属硬掩模设置在磁性隧道结（MTJ）上。 MTJ的顶部接触形成在介电层内，例如低介电常数（低k）或极低k层。 在顶部触点上方提供了另外的介电层，用于额外的连接，用于附加电路以形成三维集成电路（3D IC）。

公开(公告)号：US20160111634A1

公开(公告)日：2016-04-21

申请号：US14940996

申请日：2015-11-13

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Wei-Chuan Chen ,  Seung Kang

IPC: H01L43/10 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/10 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers. An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR. The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization.

Abstract translation: 垂直磁隧道结（MTJ）装置包括沉积在隧道势垒层和参考层之间的隧道磁阻（TMR）增强缓冲层。 在TMR增强缓冲层和参考层之间沉积非晶合金间隔物以增强TMR。 非晶合金间隔物阻挡面心立方（fcc）取向钉扎层的模板效应，并且在钉扎层和TMR增强缓冲层之间提供强耦合，以确保完全垂直磁化。

公开(公告)号：US09269893B2

公开(公告)日：2016-02-23

申请号：US14243324

申请日：2014-04-02

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Chando Park ,  Wei-Chuan Chen

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask.

Abstract translation: 用于制造磁性隧道结（MTJ）装置的多步骤蚀刻技术包括在第一蚀刻步骤中在MTJ装置的第一电极上形成第一导电硬掩模以蚀刻第一电极。 该方法还包括在第一导电硬掩模上形成第二导电硬掩模，用于在第二蚀刻步骤期间蚀刻MTJ装置的磁性层。 间隔层共形沉积在第一导电硬掩模的侧壁上。 第二导电硬掩模沉积在第一导电硬掩模上并与第一导电硬掩模的侧壁上的间隔层对准。

公开(公告)号：US09082962B2

公开(公告)日：2015-07-14

申请号：US14086054

申请日：2013-11-21

Applicant: QUALCOMM Incorporated

Inventor： Seung Hyuk Kang ,  Xia Li ,  Wei-Chuan Chen ,  Kangho Lee ,  Xiaochun Zhu ,  Wah Nam Hsu

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.

Abstract translation: 具有直接接触的磁性隧道结（MTJ）被制造成具有较低的电阻，提高的产量和更简单的制造。 较低的电阻提高了MTJ中的读取和写入过程。 MTJ层沉积在与底部金属对准的底部电极上。 蚀刻停止层可以沉积在底部金属附近，以防止围绕底部金属的绝缘体的过蚀刻。 在沉积MTJ层之前将底部电极平坦化以提供基本平坦的表面。 另外，可以在MTJ层之前的底部电极上沉​​积底层以促进MTJ的期望特性。

公开(公告)号：US09070870B2

公开(公告)日：2015-06-30

申请号：US14219026

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Xia Li ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L41/12 ,  H01F10/32 ,  H01F41/32

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/222 ,  H01L41/12 ,  H01L43/08 ,  H01L43/10

Abstract: Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current.

Abstract translation: 使用在MTJ上引起定向静态应变/应力以增加垂直磁各向异性的工艺和结构构造来构造部分垂直磁各向异性（PPMA）型磁性随机存取存储器单元。 因此，MTJ的开关电流降低。 在制造过程中，受控方向和/或受控幅度诱发MTJ上的定向静态应变/应力。 MTJ永久地受到预定的定向应力，并且永久地包括提供减小的开关电流的定向静态应变/应变。

公开(公告)号：US10740017B2

公开(公告)日：2020-08-11

申请号：US15963668

申请日：2018-04-26

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Wei-Chuan Chen ,  Sungryul Kim ,  Adam Edward Newham ,  Seung Hyuk Kang ,  Rashid Ahmed Akbar Attar

IPC: G06F3/06 ,  G11C11/00 ,  G11C29/52 ,  A61N1/372 ,  H04W4/80

Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

公开(公告)号：US10446743B2

公开(公告)日：2019-10-15

申请号：US15868367

申请日：2018-01-11

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32 ,  H01L43/10

Abstract: Double-patterned magneto-resistive random access memory (MRAM) for reducing magnetic tunnel junction (MTJ) pitch for increased MRAM bit cell density is disclosed. In one aspect, to fabricate MTJs in an MRAM array with reduced MTJ row pitch, a first patterning process is performed to provide separation areas in an MTJ layer between what will become rows of fabricated MTJs, which facilitates MTJs in a given row sharing a common bottom electrode. This reduces the etch depth and etching time needed to etch the individual MTJs in a subsequent step, can reduce lateral projections of sidewalls of the MTJs, thereby relaxing the pitch between adjacent MTJs, and may allow an initial MTJ hard mask layer to be reduced in height. A subsequent second patterning process is performed to fabricate individual MTJs. Additional separation areas are etched between free layers of adjacent MTJs in a given row to fabricate the individual MTJs.

公开(公告)号：US10249814B1

公开(公告)日：2019-04-02

申请号：US15947660

申请日：2018-04-06

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Seung Kang ,  Sungryul Kim ,  Wei-Chuan Chen

IPC: G11C11/00 ,  H01L43/02 ,  G01R33/09 ,  G11C11/16 ,  H01L43/08

Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.