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公开(公告)号：US09077289B2
公开(公告)日：2015-07-07
申请号：US13918771
申请日：2013-06-14
Applicant: QUALCOMM Incorporated
Inventor： Yu Huang , Thomas Clark Bryan , Mark Wayland
Abstract: A receiver is disclosed. The receiver includes an amplifier and a bias circuit configured to provide a bias current to the amplifier. The bias circuit is self biasing. The bias circuit is also configured to adjust the bias current using positive feedback from the amplifier.
Abstract translation: 公开了接收机。 接收机包括放大器和被配置为向放大器提供偏置电流的偏置电路。 偏置电路是自偏置的。 偏置电路还被配置为使用来自放大器的正反馈来调整偏置电流。
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公开(公告)号：US20170134191A1
公开(公告)日：2017-05-11
申请号：US15412631
申请日：2017-01-23
Applicant: QUALCOMM INCORPORATED
Inventor： Mohammed Mizanur Rahman , Thomas Clark Bryan , Jacob Stephen Schneider , Luverne Ray Peterson , Tin Tin Wee , Alvin Leng Sun Loke
CPC classification number: H04L25/03885 , H04B1/16 , H04L25/0278 , H04L25/029 , H04L25/0292 , H04L25/0298 , H04L25/03 , H04L25/03834 , H04L25/03878 , H04L25/08
Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but- for the equalizer.
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公开(公告)号：US09614703B2
公开(公告)日：2017-04-04
申请号：US14852088
申请日：2015-09-11
Applicant: QUALCOMM Incorporated
Inventor： Mohammed Mizanur Rahman , Thomas Clark Bryan , Jacob Stephen Schneider , LuVerne Ray Peterson , Tin Tin Wee , Alvin Leng Sun Loke
CPC classification number: H04L25/03885 , H04B1/16 , H04L25/0278 , H04L25/029 , H04L25/0292 , H04L25/0298 , H04L25/03 , H04L25/03834 , H04L25/03878 , H04L25/08
Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.
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公开(公告)号：US20160308519A1
公开(公告)日：2016-10-20
申请号：US15138142
申请日：2016-04-25
Applicant: QUALCOMM Incorporated
Inventor： Thomas Clark Bryan , Alvin Leng Sun Loke , Stephen Knol , Gregory Francis Lynch , Tin Tin Wee , LuVerne Ray Peterson , Yue Li
IPC: H03K5/15 , H01L23/538 , H01L25/065
CPC classification number: H03K5/15013 , G06F1/10 , G11C7/22 , H01L23/5384 , H01L23/5389 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/24137 , H01L2224/73267 , H01L2924/15311
Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.
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公开(公告)号：US20160294585A1
公开(公告)日：2016-10-06
申请号：US14852088
申请日：2015-09-11
Applicant: QUALCOMM Incorporated
Inventor： Mohammed Mizanur Rahman , Thomas Clark Bryan , Jacob Stephen Schneider , LuVerne Ray Peterson , Tin Tin Wee , Alvin Leng Sun Loke
CPC classification number: H04L25/03885 , H04B1/16 , H04L25/0278 , H04L25/029 , H04L25/0292 , H04L25/0298 , H04L25/03 , H04L25/03834 , H04L25/03878 , H04L25/08
Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but-for the equalizer.
Abstract translation: 公开了使用不匹配阻抗和均衡器来提供接收和捕获数据以节省功率的方法，系统和电路。 一种与传输线通信的数据接收机，所述数据接收机具有相对于所述传输线的特性阻抗失配的终端阻抗; 以及与数据接收器通信的均衡器，均衡器被配置为从数据接收器接收信道发送的数据信号并且重新形成信号以减小失真RC衰减; 其中所述电路被配置为以第一模式可选择地操作，其中终端阻抗相对于传输线的特性阻抗匹配，以及第二模式，其中终端阻抗相对于传输线的特性阻抗失配， 信号是不可恢复的，但是对于均衡器。
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Patent Agency Ranking
公开(公告)号：US09263107B1
公开(公告)日：2016-02-16
申请号：US14535271
申请日：2014-11-06
Applicant: QUALCOMM Incorporated
Inventor： Mark Charles Wayland , Thomas Clark Bryan , Yu Huang , Michael Joseph Brunolli
CPC classification number: G11C7/109 , G11C7/1051 , G11C7/1063 , G11C7/1066 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2029/0409 , H03K3/017 , H03K5/1565 , H03K19/018507
Abstract: A driver circuit includes an output driver including a plurality of output driver legs. The driver circuit further includes a duty cycle adjuster configured to adjust a duty cycle of a signal provided to the output driver. The driver circuit further includes an isolation module configured to isolate at least one output driver leg of the output driver legs from remaining output driver legs of the output driver legs. The driver circuit further includes a duty cycle monitor configured to monitor an output of the at least one output driver leg when the at least one output driver leg is isolated from the remaining output driver legs, and to provide the monitored output to the duty cycle adjuster.
Abstract translation: 驱动器电路包括具有多个输出驱动器支路的输出驱动器。 驱动器电路还包括占空比调整器，其被配置为调整提供给输出驱动器的信号的占空比。 驱动器电路还包括隔离模块，其被配置为将输出驱动器支路的至少一个输出驱动器支路与输出驱动器支路的剩余输出驱动器支路隔离。 驱动器电路还包括占空比监视器，其被配置为当至少一个输出驱动器支路与剩余的输出驱动器支路隔离时监视至少一个输出驱动器支路的输出，并且将所监视的输出提供给占空比调整器 。
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公开(公告)号：US20160019179A1
公开(公告)日：2016-01-21
申请号：US14335712
申请日：2014-07-18
Applicant: QUALCOMM Incorporated
Inventor： Alvin Leng Sun Loke , Tin Tin Wee , Thomas Clark Bryan
CPC classification number: G06F13/4072 , G06F13/4208
Abstract: Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus.
Abstract translation: 提供了数据总线反转（DBI）的电路和方法。 在一个示例中，DBI位的紧接之前的值会影响DBI位的下一个值。 具体地说，在某些情况下，DBI位的值被保持到DBI位的紧前一个值，以限制数据总线上的转换总数。
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公开(公告)号：US20180340977A1
公开(公告)日：2018-11-29
申请号：US15603779
申请日：2017-05-24
Applicant: QUALCOMM Incorporated
Inventor： Tapan Jyoti Chakraborty , Alvin Leng Sun Loke , Hong Dai , Thomas Clark Bryan
IPC: G01R31/3177 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31727 , G01R31/318505 , G01R31/318513 , G01R31/318533 , G01R31/318536
Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.
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公开(公告)号：US20180231608A1
公开(公告)日：2018-08-16
申请号：US15955013
申请日：2018-04-17
Applicant: QUALCOMM Incorporated
Inventor： Alvin Leng Sun Loke , Thomas Clark Bryan , Reza Jalilizeinali , Tin Tin Wee , Stephen Robert Knol , Luverne Ray Peterson
IPC: G01R31/3177 , G01R31/317 , G01R31/3185
CPC classification number: G01R31/3177 , G01R31/31716 , G01R31/318513
Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.
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公开(公告)号：US09825626B2
公开(公告)日：2017-11-21
申请号：US14792441
申请日：2015-07-06
Applicant: QUALCOMM, Incorporated
Inventor： Mohammed Mizanur Rahman , Jacob Stephen Schneider , Thomas Clark Bryan , LuVerne Ray Peterson , Gregory Francis Lynch , Alvin Leng Sun Loke
IPC: H03K17/00 , H03K17/687 , H04L25/02 , H04L25/03 , H03F3/45
CPC classification number: H03K17/687 , H03F3/45197 , H03F2203/45488 , H03F2203/45494 , H03F2203/45504 , H04L25/0272 , H04L25/0292 , H04L25/03878
Abstract: A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.
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