公开(公告)号：US09123408B2

公开(公告)日：2015-09-01

申请号：US13902705

申请日：2013-05-24

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract translation: 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。

公开(公告)号：US09734890B1

公开(公告)日：2017-08-15

申请号：US15142306

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Michael Drop ,  Vaishnav Srinivas ,  Philip Clovis

IPC: G11C11/409 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

公开(公告)号：US09734878B1

公开(公告)日：2017-08-15

申请号：US15142316

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Michael Drop ,  Vaishnav Srinivas ,  Philip Clovis

IPC: G11C7/10 ,  G11C11/408 ,  G11C11/407 ,  G11C11/4076 ,  G06F13/42 ,  G06F13/16

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

公开(公告)号：US20140347941A1

公开(公告)日：2014-11-27

申请号：US13902705

申请日：2013-05-24

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

IPC: G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract translation: 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。