公开(公告)号：US11264995B1

公开(公告)日：2022-03-01

申请号：US17079795

申请日：2020-10-26

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Chao ,  Yiwu Tang ,  Yunliang Zhu ,  Dongmin Park ,  Jingcheng Zhuang

IPC: H03B19/00 ,  H03L7/197 ,  H03L7/099 ,  H03K5/00

Abstract: A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.

公开(公告)号：US10575279B2

公开(公告)日：2020-02-25

申请号：US15088725

申请日：2016-04-01

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti Asuri ,  Jingcheng Zhuang ,  Praveen Sampath ,  Shrenik Patel ,  Jeremy Darren Dunworth ,  Lai Kan Leung ,  Gurkanwal Singh Sahota ,  Jong Min Park

IPC: H04W72/04 ,  H04L5/00 ,  H04B1/713 ,  H04B1/7136

Abstract: An apparatus comprising a transmit path, a plurality of local oscillators and a control unit. The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.

公开(公告)号：US10534025B2

公开(公告)日：2020-01-14

申请号：US15710593

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jingcheng Zhuang

IPC: G01R23/02 ,  G01R25/00 ,  H03L7/089

Abstract: A phase frequency detector (PFD) isolates supply (e.g., voltage supply) to a reference path and a feedback path of a phase locked loop (PLL) such that the power supply to the reference path is independent of the power supply to the feedback path. This isolation improves linearity. In one instance, the PFD includes a supply voltage, one or more switches, a reference capacitor and a feedback capacitor. The reference capacitor is selectively coupled to the supply voltage via the one or more switches and the feedback capacitor is selectively coupled to the supply voltage via the one or more switches.

公开(公告)号：US10523272B2

公开(公告)日：2019-12-31

申请号：US15606820

申请日：2017-05-26

Applicant: QUALCOMM Incorporated

Inventor： Madhukar Vallabhaneni ,  Girish Koppassery ,  Xinhua Chen ,  Jingcheng Zhuang

IPC: H04B3/28 ,  H04L25/08 ,  H05K1/02 ,  H01R9/03 ,  H01R9/11 ,  H01R11/05 ,  H01R12/70 ,  H01R12/77 ,  H01R12/00 ,  H04L25/00 ,  H04L25/02

Abstract: An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.

公开(公告)号：US20170094641A1

公开(公告)日：2017-03-30

申请号：US15088725

申请日：2016-04-01

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti Asuri ,  Jingcheng Zhuang ,  Praveen Sampath ,  Shrenik Patel ,  Jeremy Darren Dunworth ,  Lai Kan Leung ,  Gurkanwal Singh Sahota ,  Jong Min Park

IPC: H04W72/04 ,  H04B1/713

CPC classification number: H04W72/04 ,  H04B1/713 ,  H04B2001/71362 ,  H04L5/0044 ,  H04L5/0053 ,  H04L5/0094

Abstract: An apparatus comprising a transmit path, a plurality of local oscillators and a control unit. The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.

公开(公告)号：US20180343032A1

公开(公告)日：2018-11-29

申请号：US15606820

申请日：2017-05-26

Applicant: QUALCOMM Incorporated

Inventor： Madhukar Vallabhaneni ,  Girish Koppassery ,  Xinhua Chen ,  Jingcheng Zhuang

IPC: H04B3/28 ,  H04L25/02 ,  H04L25/08 ,  H05K1/02 ,  H01R9/03 ,  H01R12/00 ,  H01R9/11 ,  H01R11/05 ,  H01R12/70 ,  H01R12/77

CPC classification number: H04B3/28 ,  H01R9/034 ,  H01R9/11 ,  H01R11/05 ,  H01R12/00 ,  H01R12/7076 ,  H01R12/775 ,  H04L25/00 ,  H04L25/0274 ,  H04L25/085 ,  H05K1/0233

Abstract: An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.

公开(公告)号：US20180254772A1

公开(公告)日：2018-09-06

申请号：US15448657

申请日：2017-03-03

Applicant: QUALCOMM Incorporated

Inventor： Shih-Chieh Hsin ,  Med Nariman ,  Jingcheng Zhuang

IPC: H03K3/3562 ,  H03K19/0185

CPC classification number: H03K3/35625 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/018521

Abstract: A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.

公开(公告)号：US09973182B2

公开(公告)日：2018-05-15

申请号：US15265217

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Animesh Paul ,  Jingcheng Zhuang ,  Xinhua Chen ,  Ravi Sridhara

IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K5/156 ,  H03K21/02

CPC classification number: H03K5/1565 ,  H03K21/02

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

公开(公告)号：US20150301539A1

公开(公告)日：2015-10-22

申请号：US14254279

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Nam Van Dang ,  Rajeev Jain ,  Terrence Brian Remple ,  Jingcheng Zhuang ,  Mong Chit Wong

IPC: G05F1/46

CPC classification number: G05F1/468 ,  G05F3/30

Abstract: A series of current repeaters with localized feedback is provided. Each current that precedes a subsequent current repeater in the series is configured to receive a feedback current from the subsequent current repeater and generate an error signal accordingly with a differential amplifier so as to reduce current repetition errors that would otherwise result from an offset voltage in the differential amplifier.

Abstract translation: 提供了一系列具有局部反馈的电流中继器。 在串联中的随后的当前中继器之前的每个电流被配置为从随后的当前中继器接收反馈电流，并且相应地使用差分放大器产生误差信号，以便减少否则由于偏置电压而产生的电流重复误差 差分放大器。

公开(公告)号：US08928365B2

公开(公告)日：2015-01-06

申请号：US13658778

申请日：2012-10-23

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Jingcheng Zhuang ,  Yan Hu ,  Xiaoliang Bai ,  Jing Kang

IPC: H03K3/00

CPC classification number: H03K19/017554 ,  H03K19/0005

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract translation: 用于静电放电（ESD）保护的输出驱动器包括耦合在电源端子和第一差分输出端子之间的第一对堆叠金属氧化物半导体场效应晶体管（MOS）器件。 输出驱动器还包括耦合在第二差分输出端子和接地端子之间的第二对堆叠MOS器件。