公开(公告)号：US20170212581A1

公开(公告)日：2017-07-27

申请号：US15005534

申请日：2016-01-25

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Richard Stewart

IPC: G06F1/32 ,  G06F13/40 ,  G06F13/16 ,  G06F1/28 ,  G06F12/08

CPC classification number: G06F1/3296 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3253 ,  G06F1/3275 ,  G06F12/0802 ,  G06F13/16 ,  G06F13/4068 ,  G06F2212/1021 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, methods, and computer programs are disclosed for controlling power efficiency in a multi-processor system. The method comprises determining a core stall time due to memory access for one of a plurality of cores in a multi-processor system. A core execution time is determined for the one of the plurality of cores. A ratio of the core stall time versus the core execution time is calculated. The method dynamically scales a frequency vote for a memory bus based on the ratio of the core stall time versus the core execution time.

公开(公告)号：US09529397B2

公开(公告)日：2016-12-27

申请号：US13783142

申请日：2013-03-01

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/206 ,  G06F1/203 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: Some implementations provide a method for performing thermal management of an electronic device. The method determines a sensation value based on (i) a temperature of the electronic device, and (ii) a temperature rate change of the electronic device. The method associates a discomfort level from a plurality of discomfort levels, based on the determined sensation value, to the electronic device. At least one discomfort level is dynamically adjustable. The discomfort level specifies a maximum allowed activity for a processing unit of the electronic device. In some implementations, the discomfort level specifies how thermally uncomfortable the electronic device is for a user of the electronic device. In some implementations, each discomfort level from the several discomfort levels is associated with a particular range of sensation values. The sensation value is based on a user adjustable sensation model. The user adjustable sensation model is based on one of several thermal coefficient constants.

Abstract translation: 一些实现提供了一种用于执行电子设备的热管理的方法。 该方法基于（i）电子设备的温度和（ii）电子设备的温度变化来确定感觉值。 该方法基于确定的感觉值将来自多个不适等级的不适等级与电子设备相关联。 至少有一个不适等级是动态可调的。 不适等级指定电子设备的处理单元的允许活动的最大值。 在一些实施方案中，不适等级规定了电子设备对电子设备的用户的热不舒服。 在一些实施方案中，来自几个不适水平的每个不适等级与感觉值的特定范围相关联。 感觉值基于用户可调节的感觉模型。 用户可调感觉模型基于几个热系数常数之一。

公开(公告)号：US20150181208A1

公开(公告)日：2015-06-25

申请号：US14327271

申请日：2014-07-09

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Yiran Li ,  Jewon Kang

IPC: H04N19/156 ,  H04N19/154 ,  H04N19/182 ,  H04N19/196

CPC classification number: H04N19/156 ,  H04N19/103 ,  H04N19/107 ,  H04N19/154 ,  H04N19/182 ,  H04N19/196 ,  H04N19/40 ,  H04N19/42 ,  H04N19/57

Abstract: In an example, a method includes encoding video data at a first video quality using an encoding parameter, and determining an operating characteristic of one or more components of an electronic device configured to record the video data. The method also includes adjusting the encoding parameter based at least in part on the determined operating characteristic and while maintaining the first video quality, and encoding the video data at the first video quality using the adjusted encoding parameter.

Abstract translation: 在一个示例中，一种方法包括使用编码参数以第一视频质量对视频数据进行编码，以及确定被配置为记录视频数据的电子设备的一个或多个组件的操作特性。 该方法还包括至少部分地基于所确定的操作特性和在保持第一视频质量的同时调整编码参数，并且使用经调整的编码参数对第一视频质量的视频数据进行编码。

公开(公告)号：US20140195837A1

公开(公告)日：2014-07-10

申请号：US13736268

申请日：2013-01-08

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Richard Gerard Hofmann ,  Yong Ju Lee

IPC: G06F1/32

CPC classification number: G06F1/3225 ,  G06F1/3287 ,  G06F13/1668 ,  Y02D10/171

Abstract: A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices. Additionally, a current/power consumption may be obtained for each memory bank within each of the plurality of volatile memory devices. Data is then copied from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower current/power consumption than the first set of memory banks. The first set of volatile memory devices and/or first set of memory banks are then placed into a power-down state.

Abstract translation: 获得了多个易失性存储器件中的每个易失性存储器件的低功率状态电流/功率消耗。 将数据从第一组易失性存储器件复制到第二组易失性存储器件，其中第二组易失性存储器件具有比第一组易失性存储器件低的电流/功率消耗。 此外，可以为多个易失性存储器件的每一个内的每个存储器组获得电流/功率消耗。 然后将数据从第一组存储器组复制到第二组存储器件中的相同存储器件中的第二组存储器组，其中第二组存储器组具有比第一组存储器更低的电流/功率消耗 银行。 然后将第一组易失性存储器件和/或第一组存储器组置于掉电状态。

公开(公告)号：US11507423B2

公开(公告)日：2022-11-22

申请号：US16834986

申请日：2020-03-30

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Richard Gerard Hofmann

IPC: G06F9/50 ,  G06N20/00 ,  G06F13/28

Abstract: Certain aspects of the present disclosure provide a method for performing parallel data processing, including: receiving data for parallel processing from a data processing requestor; generating a plurality of data sub-blocks; determining a plurality of data portions in each data sub-block of the plurality of data sub-blocks; changing an order of the plurality of data portions in at least one data sub-block of the plurality of data sub-blocks; providing the plurality of data sub-blocks, including the at least one data sub-block comprising the changed order of the plurality of data portions, to a plurality of processing units for parallel processing; and receiving processed data associated with the plurality of data sub-blocks from the plurality of processing units.

公开(公告)号：US09927866B2

公开(公告)日：2018-03-27

申请号：US14187270

申请日：2014-02-22

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Yiran Li ,  Inho Hwang ,  Young Hoon Kang ,  Joshua Stubbs ,  Sean Sweeney ,  R. Nicholson Gibson ,  Andrew J. Frantz

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/324 ,  Y02D10/172

Abstract: A method and system for optimizing a core voltage level of a portable computing device (“PCD”) and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values is determined for a plurality of subcomponents within the PCD. Next, a reduced set of voltage values may be calculated with a voltage aggregator based on the plurality of voltage values. An optimized voltage level for a shared power domain may then be determined by a voltage optimizer within the PCD from the reduced set of voltage values. A shared power domain may then be set to the optimized voltage level. Subsequently, an operating frequency of each subcomponent may be optimized with a frequency performance enhancer based on the optimized voltage level. An optimal power collapse duration may also be calculated by the frequency performance enhancer and set for each subcomponent from the optimal frequency.

公开(公告)号：US20170293340A1

公开(公告)日：2017-10-12

申请号：US15094909

申请日：2016-04-08

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Cristian Duroiu

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3243 ,  G06F1/3265 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24

Abstract: In certain aspects, a method for frequency scaling comprises determining whether only a subset of multiple processors is active, wherein the multiple processors share one or more resources. The method also comprises increasing a frequency of at least one processor in the subset of the multiple processors if a determination is made that only the subset of the multiple processors is active and the frequency of the at least one processor is below a frequency threshold. This may be done, for example, to increase the time duration of an idle mode for the one or more shared resources and achieve an overall power reduction for a system including the multiple processors, the one or more shared resources, and/or other function blocks.

公开(公告)号：US09760149B2

公开(公告)日：2017-09-12

申请号：US13736268

申请日：2013-01-08

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Richard Gerard Hofmann ,  Yong Ju Lee

IPC: G06F1/32 ,  G06F13/16

CPC classification number: G06F1/3225 ,  G06F1/3287 ,  G06F13/1668 ,  Y02D10/171

Abstract: A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices. Additionally, a current/power consumption may be obtained for each memory bank within each of the plurality of volatile memory devices. Data is then copied from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower current/power consumption than the first set of memory banks. The first set of volatile memory devices and/or first set of memory banks are then placed into a power-down state.

公开(公告)号：US09733694B2

公开(公告)日：2017-08-15

申请号：US14839836

申请日：2015-08-28

Applicant: Qualcomm Incorporated

Inventor： Hee Jun Park ,  Krishna V. S. S. S. R. Vanka ,  Sravan Kumar Ambapuram ,  Shirish Kumar Agarwal ,  Shih-Hsin Jason Hu

IPC: G06F1/26 ,  G06F1/32 ,  H04W52/02

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/329 ,  H04W52/0251 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164

Abstract: Systems and methods for dynamically adjusting an input parameter, such as power supply level, to a shared power domain in a portable computing device are disclosed. The power domain includes a plurality of processing resources that share the power source. The power supply level is reduced based on a critical core vote pool derived from votes from the plurality of processing resources. The critical core vote pool is narrowed from all the votes by disqualifying votes based on the operating status of the associated processing resources. For example, because inactive processing resources may be unaffected by a change in the voltage level to the shared domain, and because certain active processing resources are in a position to adjust to a power change dictated by another processing resource, such processing resources may be considered noncritical and their votes disqualified from consideration.

公开(公告)号：US09697124B2

公开(公告)日：2017-07-04

申请号：US14595998

申请日：2015-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Krishna Vsssr Vanka ,  Sravan Kumar Ambapuram ,  Shirish Kumar Agarwal ,  Ashvinkumar Namjoshi ,  Harshad Bhutada

IPC: G06F12/08 ,  G06F11/34 ,  G06F9/48 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/084 ,  G06F9/4856 ,  G06F9/5016 ,  G06F11/34 ,  G06F11/3433 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.