公开(公告)号：US09697124B2

公开(公告)日：2017-07-04

申请号：US14595998

申请日：2015-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Krishna Vsssr Vanka ,  Sravan Kumar Ambapuram ,  Shirish Kumar Agarwal ,  Ashvinkumar Namjoshi ,  Harshad Bhutada

IPC: G06F12/08 ,  G06F11/34 ,  G06F9/48 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/084 ,  G06F9/4856 ,  G06F9/5016 ,  G06F11/34 ,  G06F11/3433 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.