公开(公告)号：US09244747B2

公开(公告)日：2016-01-26

申请号：US14210064

申请日：2014-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Krishna Vsssr Vanka ,  Shirish Kumar Agarwal ,  Sravan Kumar Ambapuram

IPC: G06F9/54 ,  G06F1/32

CPC classification number: G06F9/54 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/544

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

Abstract translation: 提供了允许处理器之间的动态时钟和电压调节（DCVS）感知处理器间通信的系统和方法，例如在便携式计算设备（“PCD”）中使用的处理器之间的处理器间通信。 在PCD的操作期间，在第一处理组件处接收至少一个数据分组。 此外，第一处理组件还接收关于在动态时钟和电压缩放（DCVS）下操作的第二处理组件的工作负载信息。 至少部分地基于所接收的工作负载信息，确定是否将所述至少一个数据分组从第一处理组件发送到第二处理组件或缓冲器，提供降低功耗的成本有效的能力，以及 提高了使用多核或多CPU实现DCVS算法或逻辑的PCD的电池寿命。

公开(公告)号：US09959075B2

公开(公告)日：2018-05-01

申请号：US15234025

申请日：2016-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： Krishna Vsssr Vanka ,  Narasimhan Agaram ,  Sravan Kumar Ambapuram

IPC: G06F1/32 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0893

CPC classification number: G06F3/0653 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0683 ,  G06F12/0804 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/60 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152

Abstract: Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A cache memory of the multi-core SoC not being accessed by other components of the SoC is identified and a number of dirty cache lines present in the cache memory is determined. For a low power mode of the core, an entry latency based on the number of dirty cache lines is determined, and an exit latency is determined. An entry power cost for the low power mode is also determined based on the number of dirty cache lines A determination is made whether the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost and the entry latency of the cache memory entering the first power mode.

公开(公告)号：US09697124B2

公开(公告)日：2017-07-04

申请号：US14595998

申请日：2015-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Krishna Vsssr Vanka ,  Sravan Kumar Ambapuram ,  Shirish Kumar Agarwal ,  Ashvinkumar Namjoshi ,  Harshad Bhutada

IPC: G06F12/08 ,  G06F11/34 ,  G06F9/48 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/084 ,  G06F9/4856 ,  G06F9/5016 ,  G06F11/34 ,  G06F11/3433 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.

公开(公告)号：US10514956B2

公开(公告)日：2019-12-24

申请号：US15710620

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Suryanarayana Raju Katari ,  Terance Wijesinghe ,  Amir Vajid ,  Krishna Vsssr Vanka

IPC: G06F9/46 ,  G06F9/50 ,  G06F11/34

Abstract: Performance-hint-driven dynamic resource management, including: receiving workload requirements and sensor inputs of a system; determining a new allocation for resources of the system; reconfiguring the resources of the system using the new allocation; evaluating performance of the system based on the reconfigured resources of the system; and generating performance hints based on the evaluated performance of the system.

公开(公告)号：US09678809B2

公开(公告)日：2017-06-13

申请号：US14993991

申请日：2016-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： Krishna Vsssr Vanka ,  Shirish Kumar Agarwal ,  Sravan Kumar Ambapuram

IPC: G06F9/54 ,  G06F1/32

CPC classification number: G06F9/54 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/544

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

公开(公告)号：US09652022B2

公开(公告)日：2017-05-16

申请号：US14472295

申请日：2014-08-28

Applicant: QUALCOMM INCORPORATED

Inventor： Asutosh Das ,  Krishna Vsssr Vanka ,  Sravan Kumar Ambapuram ,  Sujit Reddy Thumma

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Systems and methods that allow for dynamic quality of service (QoS) levels for an application processor in a multi-core on-chip system (SoC) in a portable computing device (PCD) are presented. During operation of the PCD an operational load of a co-processor of the SoC is determined, where the co-processor is in communication with an application processor of the SoC. Based on the determined load, the co-processor determines a QoS level required from the application processor. The QoS level is communicated to the application processor. The application processor determines whether it can implement power optimization measures, such as entering into a low power mode (LPM), based at least in part on the dynamically communicated QoS level from the co-processor. The present disclosure provides a cost effective ability to reduce power consumption in PCDs implementing one or more cores or CPUs that are dependent upon the application processor.