公开(公告)号：US09671857B2

公开(公告)日：2017-06-06

申请号：US14266642

申请日：2014-04-30

Applicant: Qualcomm Incorporated

Inventor： Krishna V. S. S. S. R Vanka ,  Hee Jun Park ,  Sravan Kumar Ambapuram ,  Shirish Kumar Agarwal

IPC: G06F1/26 ,  G06F1/32 ,  H04W52/02

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/329 ,  H04W52/0251 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164

Abstract: Systems and methods for dynamically adjusting an input parameter to a power domain in a portable computing device are disclosed. The power domain includes two or more processing resources that share a power source. Dynamic use of the two or more processing resources creates an opportunity to adjust the input parameter when a status change associated with a processing resource in the power domain occurs. A controller in the power domain includes logic that responds to a status indicator associated with a respective processing resource in the power domain by generating a control signal that directs a device to adjust one or both of input voltage and clock frequency.

公开(公告)号：US09244747B2

公开(公告)日：2016-01-26

申请号：US14210064

申请日：2014-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Krishna Vsssr Vanka ,  Shirish Kumar Agarwal ,  Sravan Kumar Ambapuram

IPC: G06F9/54 ,  G06F1/32

CPC classification number: G06F9/54 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/544

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

Abstract translation: 提供了允许处理器之间的动态时钟和电压调节（DCVS）感知处理器间通信的系统和方法，例如在便携式计算设备（“PCD”）中使用的处理器之间的处理器间通信。 在PCD的操作期间，在第一处理组件处接收至少一个数据分组。 此外，第一处理组件还接收关于在动态时钟和电压缩放（DCVS）下操作的第二处理组件的工作负载信息。 至少部分地基于所接收的工作负载信息，确定是否将所述至少一个数据分组从第一处理组件发送到第二处理组件或缓冲器，提供降低功耗的成本有效的能力，以及 提高了使用多核或多CPU实现DCVS算法或逻辑的PCD的电池寿命。

公开(公告)号：US11363501B2

公开(公告)日：2022-06-14

申请号：US16727725

申请日：2019-12-26

Applicant: QUALCOMM Incorporated

Inventor： Karthik Rangaraju ,  Shirish Kumar Agarwal ,  Narasimhan Venkata Agaram

IPC: H04W36/00 ,  H04W12/037

Abstract: This disclosure provides systems, methods and apparatuses for intelligent connectivity switching techniques. The techniques include, for example, determining that a wireless connection is encrypted, and in response to determining that the wireless connection is encrypted, employing one or more intelligent connectivity switching mechanisms to ensure a desirable level of user experience may be maintained and data stall conditions may be avoided or overcome. When a wireless station is in an area where two radio access technology (RAT) connections are present, the intelligent connectivity switching mechanisms can include responding to a user interface prompt, evaluating one or more signal-to-noise (SNR)-related metrics, or comparing an application, task or activity to a whitelist.

公开(公告)号：US09733694B2

公开(公告)日：2017-08-15

申请号：US14839836

申请日：2015-08-28

Applicant: Qualcomm Incorporated

Inventor： Hee Jun Park ,  Krishna V. S. S. S. R. Vanka ,  Sravan Kumar Ambapuram ,  Shirish Kumar Agarwal ,  Shih-Hsin Jason Hu

IPC: G06F1/26 ,  G06F1/32 ,  H04W52/02

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/329 ,  H04W52/0251 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164

Abstract: Systems and methods for dynamically adjusting an input parameter, such as power supply level, to a shared power domain in a portable computing device are disclosed. The power domain includes a plurality of processing resources that share the power source. The power supply level is reduced based on a critical core vote pool derived from votes from the plurality of processing resources. The critical core vote pool is narrowed from all the votes by disqualifying votes based on the operating status of the associated processing resources. For example, because inactive processing resources may be unaffected by a change in the voltage level to the shared domain, and because certain active processing resources are in a position to adjust to a power change dictated by another processing resource, such processing resources may be considered noncritical and their votes disqualified from consideration.

公开(公告)号：US09697124B2

公开(公告)日：2017-07-04

申请号：US14595998

申请日：2015-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Krishna Vsssr Vanka ,  Sravan Kumar Ambapuram ,  Shirish Kumar Agarwal ,  Ashvinkumar Namjoshi ,  Harshad Bhutada

IPC: G06F12/08 ,  G06F11/34 ,  G06F9/48 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/084 ,  G06F9/4856 ,  G06F9/5016 ,  G06F11/34 ,  G06F11/3433 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.

公开(公告)号：US09678809B2

公开(公告)日：2017-06-13

申请号：US14993991

申请日：2016-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： Krishna Vsssr Vanka ,  Shirish Kumar Agarwal ,  Sravan Kumar Ambapuram

IPC: G06F9/54 ,  G06F1/32

CPC classification number: G06F9/54 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/544

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.