公开(公告)号：US10949278B2

公开(公告)日：2021-03-16

申请号：US16018575

申请日：2018-06-26

Applicant: QUALCOMM Incorporated

Inventor： Asutosh Das ,  Vijay Viswanath ,  Ritesh Harjani ,  Srinivasan Karunelli

IPC: G06F11/00 ,  G06F11/07 ,  G06F3/06 ,  G06F12/02 ,  G06F1/3234

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for communicating error information during memory operations. For example, certain aspects of the present disclosure may provide a method for memory operations. The method generally including receiving a command from a host device, performing memory operations corresponding to the command received from the host device, detecting an error during the memory operations, and communicating the error based on the detection, wherein the error is communicated before receiving another command from the host device.

公开(公告)号：US09652022B2

公开(公告)日：2017-05-16

申请号：US14472295

申请日：2014-08-28

Applicant: QUALCOMM INCORPORATED

Inventor： Asutosh Das ,  Krishna Vsssr Vanka ,  Sravan Kumar Ambapuram ,  Sujit Reddy Thumma

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Systems and methods that allow for dynamic quality of service (QoS) levels for an application processor in a multi-core on-chip system (SoC) in a portable computing device (PCD) are presented. During operation of the PCD an operational load of a co-processor of the SoC is determined, where the co-processor is in communication with an application processor of the SoC. Based on the determined load, the co-processor determines a QoS level required from the application processor. The QoS level is communicated to the application processor. The application processor determines whether it can implement power optimization measures, such as entering into a low power mode (LPM), based at least in part on the dynamically communicated QoS level from the co-processor. The present disclosure provides a cost effective ability to reduce power consumption in PCDs implementing one or more cores or CPUs that are dependent upon the application processor.