知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.015 seconds)

    Energy efficiency aware thermal management in a multi-processor system on a chip
    4.
    发明授权
    Energy efficiency aware thermal management in a multi-processor system on a chip 有权
    芯片上多处理器系统中的节能意识热管理

    公开(公告)号：US09582012B2

    公开(公告)日：2017-02-28

    申请号：US14280629

    申请日：2014-05-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： Hee Jun Park ,  Young Hoon Kang ,  Ronald Frank Alton ,  Christoper Lee Medrano ,  Jon James Anderson

    IPC: G06F1/32 ,  G05D23/19 ,  G05B15/02 ,  G06F1/20 ,  G06F1/26

    CPC classification number: G05D23/1917 ,  G05B15/02 ,  G06F1/203 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34 ,  Y02D10/16

    Abstract: Various embodiments of methods and systems for energy efficiency aware thermal management in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, energy efficiency aware thermal management techniques that compare performance data of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by adjusting the power supplies to, reallocating workloads away from, or transitioning the power mode of, the least energy efficient processing components. In these ways, embodiments of the solution optimize the average amount of power consumed across the SoC to process a MIPS of workload.

    Abstract translation: 公开了在包含芯片上的异构多处理器系统（“SoC”）的便携式计算设备中的用于能量效率感知热管理的方法和系统的各种实施例。 由于异构多处理器SoC中的单独处理组件可能在给定温度下可能表现出不同的处理效率，因此可以利用能源效率感知热管理技术来比较其测量工作温度下各个处理组件的性能数据，从而优化服务质量 （“QoS”），通过调整电力供应，重新分配工作量远离或转移最低能效处理组件的功率模式。 以这些方式，该解决方案的实施例优化了跨SoC消耗的平均功耗量以处理MIPS的工作负载。

    FORCED COMPRESSION OF SINGLE I2C WRITES
    5.
    发明申请
    FORCED COMPRESSION OF SINGLE I2C WRITES 审中-公开

    公开(公告)号：US20180196770A1

    公开(公告)日：2018-07-12

    申请号：US15403559

    申请日：2017-01-11

    Applicant: QUALCOMM Incorporated

    Inventor： Inyoung Woo ,  Young Hoon Kang

    IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/364 ,  G06F13/404 ,  G06F13/4282 ,  G06F13/4291

    Abstract: Systems, methods, and apparatus are described that enable a physical layer interface of a device coupled to a serial bus to combine two or more single-byte write transactions to obtain a multi-byte write transaction. A method includes buffering a first single-byte transaction addressed to a first register at a first address of a slave device in a first-in-first-out buffer of the physical layer, receiving at the physical layer a second single-byte transaction addressed to a second register at a second address of the slave device coupled to the serial bus, determining in the physical layer whether the second address is incrementally greater than the first address, combining the second single-byte transaction with the first single-byte transaction to obtain a multi-byte transaction, replacing the first single-byte transaction with the multi-byte transaction in the first-in-first-out buffer, and transmitting a sequence of transactions output by the first-in-first-out buffer over the serial bus.

    CPU/GPU DCVS co-optimization for reducing power consumption in graphics frame processing
    7.
    发明授权
    CPU/GPU DCVS co-optimization for reducing power consumption in graphics frame processing 有权
    CPU / GPU DCVS协同优化，以降低图形帧处理中的功耗

    公开(公告)号：US09378536B2

    公开(公告)日：2016-06-28

    申请号：US14266685

    申请日：2014-04-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： Hee Jun Park ,  Young Hoon Kang ,  Mriganka Mondal

    IPC: G06F1/32 ,  G06T1/20

    CPC classification number: G06T1/20 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G09G2330/021 ,  G09G2360/06 ,  Y02D10/126 ,  Y02D10/172

    Abstract: Systems, methods, and computer programs are disclosed for minimizing power consumption in graphics frame processing. One such method comprises: initiating graphics frame processing to be cooperatively performed by a central processing unit (CPU) and a graphics processing unit (GPU); receiving CPU activity data and GPU activity data; determining a set of available dynamic clock and voltage/frequency scaling (DCVS) levels for the GPU and the CPU; and selecting from the set of available DCVS levels an optimal combination of a GPU DCVS level and a CPU DCVS level, based on the CPU and GPU activity data, which minimizes a combined power consumption of the CPU and the GPU during the graphics frame processing.

    Abstract translation: 公开了用于使图形帧处理中的功率消耗最小化的系统，方法和计算机程序。 一种这样的方法包括：启动由中央处理单元（CPU）和图形处理单元（GPU）协同执行的图形帧处理; 接收CPU活动数据和GPU活动数据; 确定用于GPU和CPU的一组可用动态时钟和电压/频率缩放（DCVS）电平; 以及基于CPU和GPU活动数据，从可用DCVS级别中选择GPU DCVS级别和CPU DCVS级别的最佳组合，其在图形帧处理期间最小化CPU和GPU的组合功耗。

    Image stabilization using machine learning
    8.
    发明授权
    Image stabilization using machine learning 有权

    公开(公告)号：US11277562B2

    公开(公告)日：2022-03-15

    申请号：US16995546

    申请日：2020-08-17

    Applicant: QUALCOMM Incorporated

    Inventor： Young Hoon Kang ,  Hee Jun Park ,  Tauseef Kazi ,  Ron Gaizman ,  Eran Pinhasov ,  Meir Tzur

    IPC: H04N5/232 ,  G06N3/08

    Abstract: Techniques and systems are provided for machine-learning based image stabilization. In some examples, a system obtains a sequence of frames captured by an image capture device during a period of time, and collects motion sensor measurements calculated by a motion sensor associated with the image capture device based on movement of the image capture device during the period of time. The system generates, using a deep learning network and the motion sensor measurements, parameters for counteracting motions in one or more frames in the sequence of frames, the motions resulting from the movement of the image capture device during the period of time. The system then adjusts the one or more frames in the sequence of frames according to the parameters to generate one or more adjusted frames having a reduction in at least some of the motions in the one or more frames.

    Image stabilization using machine learning
    9.
    发明授权
    Image stabilization using machine learning 有权

    公开(公告)号：US10771698B2

    公开(公告)日：2020-09-08

    申请号：US16120037

    申请日：2018-08-31

    Applicant: QUALCOMM Incorporated

    Inventor： Young Hoon Kang ,  Hee Jun Park ,  Tauseef Kazi ,  Ron Gaizman ,  Eran Pinhasov ,  Meir Tzur

    IPC: H04N5/232 ,  G06N3/08

    Abstract: Techniques and systems are provided for machine-learning based image stabilization. In some examples, a system obtains a sequence of frames captured by an image capture device during a period of time, and collects motion sensor measurements calculated by a motion sensor associated with the image capture device based on movement of the image capture device during the period of time. The system generates, using a deep learning network and the motion sensor measurements, parameters for counteracting motions in one or more frames in the sequence of frames, the motions resulting from the movement of the image capture device during the period of time. The system then adjusts the one or more frames in the sequence of frames according to the parameters to generate one or more adjusted frames having a reduction in at least some of the motions in the one or more frames.

    Forced compression of single I2C writes
    10.
    发明授权
    Forced compression of single I2C writes 有权

    公开(公告)号：US10169273B2

    公开(公告)日：2019-01-01

    申请号：US15403559

    申请日：2017-01-11

    Applicant: QUALCOMM Incorporated

    Inventor： Inyoung Woo ,  Young Hoon Kang

    IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40

    Abstract: Systems, methods, and apparatus are described that enable a physical layer interface of a device coupled to a serial bus to combine two or more single-byte write transactions to obtain a multi-byte write transaction. A method includes buffering a first single-byte transaction addressed to a first register at a first address of a slave device in a first-in-first-out buffer of the physical layer, receiving at the physical layer a second single-byte transaction addressed to a second register at a second address of the slave device coupled to the serial bus, determining in the physical layer whether the second address is incrementally greater than the first address, combining the second single-byte transaction with the first single-byte transaction to obtain a multi-byte transaction, replacing the first single-byte transaction with the multi-byte transaction in the first-in-first-out buffer, and transmitting a sequence of transactions output by the first-in-first-out buffer over the serial bus.

Patent Agency Ranking