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    Intelligent Multicore Control For Optimal Performance Per Watt
    1.
    发明申请
    Intelligent Multicore Control For Optimal Performance Per Watt 有权
    智能多核控制优化每瓦特性能

    公开(公告)号：US20150046685A1

    公开(公告)日：2015-02-12

    申请号：US14074908

    申请日：2013-11-08

    Applicant: QUALCOMM Incorporated

    Inventor： Hee-Jun Park ,  Steven S. Thomson ,  Ronald Frank Alton ,  Edoardo Regini ,  Satish Goverdhan ,  Pieter-Louis Dam Backer

    IPC: G06F9/38

    CPC classification number: G06F9/38 ,  G06F1/206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22

    Abstract: The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget.

    Abstract translation: 各方面提供了用于多核集成电路的多个处理器核的智能多核控制的装置和方法。 这些方面可以识别和激活一组最优化的处理器内核，以实现给定工作负载的最低级别功耗或给定功率预算的最高性能。 处理器核心的最佳集合可以是活动处理器核心的数量或特定活动处理器核心的指定。 当处理器核心的温度读数低于阈值时，可以选择一组处理器核以为给定的工作负载提供最低的功耗。 当处理器核心的温度读数高于阈值时，可以选择设置的处理器核心以为给定的功率预算提供最佳性能。

    Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power
    2.
    发明授权
    Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power 有权
    优化核心测序的算法可最大限度地提高性能并降低芯片的温度和功率

    公开(公告)号：US09557797B2

    公开(公告)日：2017-01-31

    申请号：US14319393

    申请日：2014-06-30

    Applicant: QUALCOMM Incorporated

    Inventor： Rajat Mittal ,  Mehdi Saeidi ,  Tao Xue ,  Ronald Frank Alton ,  Rajit Chandra ,  Sachin Dasnurkar

    IPC: G06F1/32 ,  G06F9/50

    CPC classification number: G06F1/3234 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D10/24

    Abstract: Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

    Abstract translation: 方面包括用于为计算设备的状态选择优选处理器核心组合的计算设备，系统和方法。 在一方面，可以确定包含多核处理器的计算设备的状态。 可以通过将处理器核心的当前泄漏与其他处理器核心的当前泄漏进行比较来确定多个电流泄漏比。 可以将这些比率与各个不等式中的计算装置的状态的边界进行比较。 响应于确定相应的不等式是真实的，可以选择与多个边界相关联的处理器核心。 边界可以与被认为对于计算设备的相关状态优选的一组处理器核心相关联。 存在于真正不等式的每个边界的处理器核心集合中的处理器核心可以是所选择的处理器核心。

    Algorithm For Preferred Core Sequencing To Maximize Performance And Reduce Chip Temperature And Power
    3.
    发明申请
    Algorithm For Preferred Core Sequencing To Maximize Performance And Reduce Chip Temperature And Power 有权
    优化核心排序的算法以最大限度地提高性能并降低芯片温度和功率

    公开(公告)号：US20150338902A1

    公开(公告)日：2015-11-26

    申请号：US14319393

    申请日：2014-06-30

    Applicant: QUALCOMM Incorporated

    Inventor： Rajat MITTAL ,  Mehdi Saeidi ,  Tao Xue ,  Ronald Frank Alton ,  Rajit Chandra ,  Sachin Dasnurkar

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D10/24

    Abstract: Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

    Abstract translation: 方面包括用于为计算设备的状态选择优选处理器核心组合的计算设备，系统和方法。 在一方面，可以确定包含多核处理器的计算设备的状态。 可以通过将处理器核心的当前泄漏与其他处理器核心的当前泄漏进行比较来确定多个电流泄漏比。 可以将这些比率与各个不等式中的计算装置的状态的边界进行比较。 响应于确定相应的不等式是真实的，可以选择与多个边界相关联的处理器核心。 边界可以与被认为对于计算设备的相关状态优选的一组处理器核心相关联。 存在于真正不等式的每个边界的处理器核心集合中的处理器核心可以是所选择的处理器核心。

    Energy efficiency aware thermal management in a multi-processor system on a chip
    5.
    发明授权
    Energy efficiency aware thermal management in a multi-processor system on a chip 有权
    芯片上多处理器系统中的节能意识热管理

    公开(公告)号：US09582012B2

    公开(公告)日：2017-02-28

    申请号：US14280629

    申请日：2014-05-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： Hee Jun Park ,  Young Hoon Kang ,  Ronald Frank Alton ,  Christoper Lee Medrano ,  Jon James Anderson

    IPC: G06F1/32 ,  G05D23/19 ,  G05B15/02 ,  G06F1/20 ,  G06F1/26

    CPC classification number: G05D23/1917 ,  G05B15/02 ,  G06F1/203 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34 ,  Y02D10/16

    Abstract: Various embodiments of methods and systems for energy efficiency aware thermal management in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, energy efficiency aware thermal management techniques that compare performance data of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by adjusting the power supplies to, reallocating workloads away from, or transitioning the power mode of, the least energy efficient processing components. In these ways, embodiments of the solution optimize the average amount of power consumed across the SoC to process a MIPS of workload.

    Abstract translation: 公开了在包含芯片上的异构多处理器系统（“SoC”）的便携式计算设备中的用于能量效率感知热管理的方法和系统的各种实施例。 由于异构多处理器SoC中的单独处理组件可能在给定温度下可能表现出不同的处理效率，因此可以利用能源效率感知热管理技术来比较其测量工作温度下各个处理组件的性能数据，从而优化服务质量 （“QoS”），通过调整电力供应，重新分配工作量远离或转移最低能效处理组件的功率模式。 以这些方式，该解决方案的实施例优化了跨SoC消耗的平均功耗量以处理MIPS的工作负载。

    Intelligent multicore control for optimal performance per watt
    9.
    发明授权
    Intelligent multicore control for optimal performance per watt 有权
    智能多核控制，实现每瓦最佳性能

    公开(公告)号：US09292293B2

    公开(公告)日：2016-03-22

    申请号：US14074908

    申请日：2013-11-08

    Applicant: QUALCOMM Incorporated

    Inventor： Hee-Jun Park ,  Steven S Thomson ,  Ronald Frank Alton ,  Edoardo Regini ,  Satish Goverdhan ,  Pieter-Louis Dam Backer

    IPC: G06F1/32 ,  G06F9/38 ,  G06F1/20 ,  G06F9/50

    CPC classification number: G06F9/38 ,  G06F1/206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22

    Abstract: The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget.

    Abstract translation: 各方面提供了用于多核集成电路的多个处理器核的智能多核控制的装置和方法。 这些方面可以识别和激活一组最优化的处理器内核，以实现给定工作负载的最低级别功耗或给定功率预算的最高性能。 处理器核心的最佳集合可以是活动处理器核心的数量或特定活动处理器核心的指定。 当处理器核心的温度读数低于阈值时，可以选择一组处理器核以为给定的工作负载提供最低的功耗。 当处理器核心的温度读数高于阈值时，可以选择设置的处理器核心以为给定的功率预算提供最佳性能。

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