公开(公告)号：US20180331061A1

公开(公告)日：2018-11-15

申请号：US15843865

申请日：2017-12-15

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Lily Zhao ,  Wei Wang ,  Ahmer Syed

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L24/13 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/56 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0221 ,  H01L2224/02215 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/16238 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/0544 ,  H01L2924/00012 ,  H01L2924/07025 ,  H01L2924/01028 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A device comprising a semiconductor die and a redistribution portion coupled to the semiconductor die. The redistribution portion includes a passivation layer and a redistribution interconnect comprising a first surface and a second surface opposite to the first surface. The redistribution interconnect is formed over the passivation layer such that the first surface is over the passivation layer and the second surface is free of contact with any passivation layer. The device includes a bump interconnect coupled to the second surface of the redistribution interconnect. In some implementations, the bump interconnect comprises a surface that faces the redistribution interconnect, and wherein an entire surface of the bump interconnect that faces the redistribution interconnect is free of contact with the passivation layer.

公开(公告)号：US12113038B2

公开(公告)日：2024-10-08

申请号：US17027316

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Hung-Yuan Hsu ,  Yangyang Sun ,  Wei Hu ,  Wei Wang ,  Lily Zhao

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/13027 ,  H01L2924/35

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

公开(公告)号：US11948909B2

公开(公告)日：2024-04-02

申请号：US17574360

申请日：2022-01-12

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Dongming He ,  Lily Zhao

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/73 ,  H01L24/26 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/33 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13082 ,  H01L2224/16148 ,  H01L2224/26125 ,  H01L2224/2919 ,  H01L2224/301 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

公开(公告)号：US20240079352A1

公开(公告)日：2024-03-07

申请号：US17929408

申请日：2022-09-02

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  Lily Zhao ,  Dongming He

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/642 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16235 ,  H01L2224/17163 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/19041 ,  H01L2924/30101 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: Aspects disclosed herein include integrated circuit (IC) packages employing a capacitor interposer substrate with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies (“dies”) electrically coupled to a package substrate that supports electrical signal routing to and from the die(s). The capacitor interposer substrate is disposed between the die(s) and the package substrate. The die(s) is coupled to embedded capacitor(s) in the capacitor interposer substrate through die interconnects coupled to external interconnects of the capacitor interposer substrate. In exemplary aspects, the external interconnects on the outer surfaces of the capacitor interposer substrate are aligned. In this manner, the capacitor interposer substrate can maintain interconnect compatibility to the die(s) and package substrate if the die(s) and package substrate have a pattern of die interconnects and external interconnects that are designed to align with each other when coupled to each other.

公开(公告)号：US09406649B2

公开(公告)日：2016-08-02

申请号：US14598053

申请日：2015-01-15

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

公开(公告)号：US20150155265A1

公开(公告)日：2015-06-04

申请号：US14598053

申请日：2015-01-15

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract translation: 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。