公开(公告)号：US09473165B2

公开(公告)日：2016-10-18

申请号：US14465650

申请日：2014-08-21

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Sameer Wadhwa ,  Dinesh Jagannath Alladi ,  Kentaro Yamamoto ,  Xiaoke Wen ,  Masoud Ensafdaran ,  Weihua Chen

IPC: H03M1/66 ,  H03M1/72 ,  H03M1/80 ,  H03M1/06

CPC classification number: H03M1/72 ,  H03M1/0612 ,  H03M1/66 ,  H03M1/804 ,  H03M1/806

Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Abstract translation: 降低对CDAC的参考电压的信号依赖性包括：将去耦电容器分成尺寸小于去耦电容器的尺寸的多个电容器; 在转换阶段期间将耦合到参考电压的采样缓冲器中的至少一个电容器隔离; 并且在每个转换步骤中使用电荷泵提供在CDAC中由电容器吸收的电荷所需的适当量的电荷，以将虚拟电荷泵送到CDAC，使得CDAC的所得结构为每个代码绘制基本相似的电荷量 更改每个转换步骤。

公开(公告)号：US09425818B1

公开(公告)日：2016-08-23

申请号：US14724555

申请日：2015-05-28

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Dinesh Jagannath Alladi ,  Liang Dai

IPC: H03M3/00

CPC classification number: H03M3/426 ,  H03M1/466 ,  H03M3/32 ,  H03M3/436

Abstract: An analog-to-digital converter includes: a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; a noise shaping module configured to compare the first input signal to the second input signal received, and to output a digital output signal and a residue signal in a first phase of a noise shaping operation; and a storage module configured to store the residue signal during the first phase of the noise shaping operation, the storage module configured to receive an analog input signal and remove the residue signal from the analog input signal in a second phase of the noise shaping operation to output a new first input signal to the noise shaping module.

Abstract translation: 模数转换器包括：第一输入端，用于接收第一输入信号; 第二输入端子，用于接收第二输入信号; 噪声整形模块，其被配置为将所述第一输入信号与所接收的所述第二输入信号进行比较，并且在噪声整形操作的第一阶段中输出数字输出信号和残留信号; 以及存储模块，被配置为在所述噪声整形操作的第一阶段期间存储所述残留信号，所述存储模块被配置为在所述噪声整形操作的第二阶段中接收模拟输入信号并从所述模拟输入信号中去除所述残留信号， 向噪声整形模块输出新的第一输入信号。

公开(公告)号：US09306553B2

公开(公告)日：2016-04-05

申请号：US13787590

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Wei Zheng ,  Dinesh Jagannath Alladi ,  Yuhua Guo

IPC: H03L5/00 ,  H03K5/156 ,  H03K3/012 ,  H03K3/356 ,  H03K19/017 ,  H03K19/0185

CPC classification number: H03K5/1565 ,  H03K3/012 ,  H03K3/35613 ,  H03K19/01714 ,  H03K19/018521 ,  H03L5/00

Abstract: Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.

Abstract translation: 本公开的某些方面提供了采用低等待时间交流耦合升压电路的电压电平移位电路，以及包括这种电平转换电路的其它电路和装置。 与常规电平转换器相比，这种电平移位电路提供显着更低的等待时间（例如，延迟减少至少两倍）。 与模拟角相比，提供一致的延迟，与此相比，电平移位电路与常规电平转换器相比，也提供了显着更低的功耗和减少的占空比失真。

公开(公告)号：US20160065232A1

公开(公告)日：2016-03-03

申请号：US14475852

申请日：2014-09-03

Applicant: QUALCOMM INCORPORATED

Inventor： Elias Hani Dagher ,  Kentaro Yamamoto ,  Dinesh Jagannath Alladi

IPC: H03M1/34

CPC classification number: H03M1/34 ,  H03M3/30 ,  H03M3/37 ,  H03M3/426 ,  H03M3/454 ,  H03M3/458 ,  H03M3/464

Abstract: In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

Abstract translation: 在一个实施例中，电路包括被配置为将模拟输入信号转换成数字信号的量化器。 量化器包括第一反馈路径，其包括从量化器的输出耦合到耦合到量化器的输入的求和结点的第一数模转换器（DAC）。 第一反馈路径将数字信号转换为第一对应的模拟值，以与求和点处的模拟输入信号组合。 此外，量化器还包括耦合到求和点的多个过剩环路延迟（ELD）补偿路径，其被配置为补偿从量化器的输出耦合到从量化器经由环路滤波器输入的第二反馈路径的过多的环路延迟。 第二反馈路径中的第二DAC将数字信号转换为第二对应的模拟值，以与模拟输入信号组合。

公开(公告)号：US20150244385A1

公开(公告)日：2015-08-27

申请号：US14549445

申请日：2014-11-20

Applicant: QUALCOMM Incorporated

Inventor： Dinesh Jagannath Alladi ,  Omar Hafiz ,  Elias Hani Dagher

IPC: H03M1/06 ,  H03M1/18 ,  H03M1/12

CPC classification number: H03M1/0629 ,  H03M1/1245 ,  H03M1/186 ,  H03M3/344

Abstract: In embodiments, a circuit includes a single-ended input coupled to a first input of a differential filter. The differential filter is coupled to an analog to digital converter (ADC), and the single-ended input includes an input DC bias voltage level and an input signal. A reference generator circuit is coupled to a second input of the differential filter. The reference generator circuit generates a reference bias voltage. The differential filter includes a first filter coupled to the singled ended input and to the ADC and a second filter coupled to the reference generator circuit and to the ADC. The first filter is configured to receive the input DC bias voltage level and input signal. The second filter is configured to receive the reference bias voltage.

Abstract translation: 在实施例中，电路包括耦合到差分滤波器的第一输入的单端输入。 差分滤波器耦合到模数转换器（ADC），单端输入包括输入直流偏置电压电平和输入信号。 参考发生器电路耦合到差分滤波器的第二输入端。 参考发生器电路产生参考偏置电压。 差分滤波器包括耦合到单端输入和ADC的第一滤波器以及耦合到参考发生器电路和ADC的第二滤波器。 第一个滤波器配置为接收输入的直流偏置电压电平和输入信号。 第二滤波器被配置为接收参考偏置电压。

公开(公告)号：US20230100825A1

公开(公告)日：2023-03-30

申请号：US17484581

申请日：2021-09-24

Applicant: Qualcomm Incorporated

Inventor： Seyed Arash Mirhaj ,  Lei Sun ,  Yuhua Guo ,  Elias Dagher ,  Aram Akhavan ,  Yan Wang ,  Dinesh Jagannath Alladi

IPC: H03M1/16 ,  H03M1/38

Abstract: An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

公开(公告)号：US10461762B1

公开(公告)日：2019-10-29

申请号：US16051686

申请日：2018-08-01

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Meysam Zargham ,  Yan Wang ,  Li Lu ,  Dinesh Jagannath Alladi

IPC: H03M1/06 ,  H03M1/00

Abstract: Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.

公开(公告)号：US10277241B1

公开(公告)日：2019-04-30

申请号：US15961631

申请日：2018-04-24

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Elias Dagher ,  Yan Wang ,  Dinesh Jagannath Alladi

IPC: H03M1/18 ,  H03M1/66 ,  H03M3/00

Abstract: A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.

公开(公告)号：US09628103B2

公开(公告)日：2017-04-18

申请号：US14639534

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yan Wang ,  Dinesh Jagannath Alladi ,  Chieh-Yu Hsieh ,  Elias Hani Dagher

IPC: H03M3/00

CPC classification number: H03M3/32 ,  H03M3/354 ,  H03M3/392 ,  H03M3/45 ,  H03M3/454 ,  H03M3/496

Abstract: A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

公开(公告)号：US09411987B2

公开(公告)日：2016-08-09

申请号：US14826928

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Dinesh Jagannath Alladi ,  Yuhua Guo

IPC: H03M3/00 ,  G06G7/186

CPC classification number: G06G7/186 ,  G06G7/1865 ,  H03M3/32 ,  H03M3/342 ,  H03M3/344 ,  H03M3/496 ,  H03M3/50

Abstract: Certain aspects of the present disclosure provide various sampling networks for switched-capacitor integrators, which may be used in switched-capacitor analog-to-digital converters (ADCs). Rather than having both an input sampling capacitor and a reference sampling capacitor, certain aspects of the present disclosure use a shared sampling capacitor for the reference voltage and the input voltage, thereby reducing ADC input-referred noise, decreasing op amp area and power, and avoiding anti-aliasing filter insertion loss. Furthermore, by sampling the reference voltage during the sampling phase and sampling the input voltage during the integration phase using the shared sampling capacitor, a high-bandwidth reference buffer need not be used for the reference voltage.

Abstract translation: 本公开的某些方面提供用于开关电容器积分器的各种采样网络，其可用于开关电容器模数转换器（ADC）。 不同于输入采样电容器和参考采样电容器两者，本公开的某些方面使用共享采样电容器作为参考电压和输入电压，从而减少ADC输入参考噪声，降低运算放大器面积和功率，以及 避免抗混叠滤波器插入损耗。 此外，通过在采样阶段对参考电压进行采样并使用共享采样电容在积分阶段对输入电压进行采样，高参考电压不需要用于参考电压。