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公开(公告)号：US10778233B1
公开(公告)日：2020-09-15
申请号：US16540829
申请日：2019-08-14
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann
Abstract: A method for Phase Locked Loop (PLL) lock detection includes determining a phase error by comparing a feedback phase to a reference phase. A frequency error is determined by comparing a feedback frequency to a reference frequency. A lock signal is determined in response to the phase error being less than an upper phase threshold and greater than a lower phase threshold, and the frequency error being less than an upper frequency threshold and greater than a lower frequency threshold.
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公开(公告)号：US10382045B2
公开(公告)日：2019-08-13
申请号：US15377917
申请日：2016-12-13
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann
Abstract: An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.
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公开(公告)号：US09337850B2
公开(公告)日：2016-05-10
申请号：US14446568
申请日：2014-07-30
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann
CPC classification number: H03L7/0994 , H03L7/099 , H03L7/0991 , H03L7/104 , H03L2207/06 , H03L2207/50
Abstract: Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.
Abstract translation: 锁相环（ADPLL）可以减少或消除建立时间。 振荡器模型提供适用于补偿频率响应和相位响应的适当设置。 硬件设备可以包括数字控制振荡器（DCO）; 以及具有处理器的DCO模型设备，其中所述处理器被配置为通过基于所述DCO的操作参数搜索所述频率来计算所述DCO的频率，将所计算的频率与测量的频率进行比较，并且基于所述比较来补偿 ，ADPLL来减少建立时间。
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公开(公告)号：US12216226B2
公开(公告)日：2025-02-04
申请号：US17661944
申请日：2022-05-04
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Cristian Pavao Moreira , Andreas Johannes Köllmann
Abstract: Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).
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公开(公告)号：US12063045B2
公开(公告)日：2024-08-13
申请号：US17451567
申请日：2021-10-20
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Jan-Peter Schat , Tim Lauber
CPC classification number: H03L7/0991 , H03L7/093
Abstract: The disclosure relates to monitoring of feedback systems such as phase lock loops. A system is disclosed, comprising: a feedback circuit (100); and a monitoring module (190). The monitoring module (190) is configured to: i) receive actual values of at least one state variable describing the state of the feedback circuit at a first time; ii) determine a predicted future value of the at least one state variable at a second time from the actual values at the first time using a model of the feedback circuit; iii) receive actual values of the at least one state variable at the second time; iv) compare the predicted future value of the at least one state variable at the second time with the actual value of the at least one state variable at the second time; and v) determine whether the feedback circuit has a fault condition, depending on the results of step iv).
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Patent Agency Ranking
公开(公告)号：US20240085476A1
公开(公告)日：2024-03-14
申请号：US17943288
申请日：2022-09-13
Applicant: NXP B.V.
Inventor： Andreas Johannes Köllmann , Ulrich Moehlmann
IPC: G01R31/317 , G01R31/3177 , G01R31/319
CPC classification number: G01R31/31727 , G01R31/3177 , G01R31/31922 , H03K5/1565
Abstract: A system includes a phase-shift to duty-cycle converter and a low pass filter. The phase-shift to duty-cycle converter has a first input for a reference clock and a second input for a phase-shifted clock that is phase-shifted relative to the reference clock. The low pass filter has an input coupled to an output of the phase-shift to duty-cycle converter and an output for an output signal. In some implementations, the phase-shift to duty-cycle converter includes a simple logic gate and a reset-set flip flop. The simple logic gate has a third input coupled to the first input and a fourth input coupled to the second input, and the reset-set flip flop has a fifth input coupled to the first input and a sixth input coupled to the second input. The low pass filter is coupled to the output of one of the simple logic gate and the reset-set flip flop.
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公开(公告)号：US20220365173A1
公开(公告)日：2022-11-17
申请号：US17661944
申请日：2022-05-04
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Cristian Pavao Moreira , Andreas Johannes Köllmann
Abstract: Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).
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公开(公告)号：US10826505B1
公开(公告)日：2020-11-03
申请号：US16449711
申请日：2019-06-24
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann , Andreas Johannes Köllmann , Christian Scherner
Abstract: A hardware device includes a frequency lock loop (FLL) that includes a phase loop filter, and a phase lock loop (PLL) such as an all digital PLL (ADPLL) that includes a frequency loop filter. A controller provides a first control signal to the FLL and a second control signal to the PLL when the device operates the same. The device can also include a digital controlled oscillator (DCO) and part of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a divider receive an input from the DCO. The controller forms a first loop with the first filter, the TDC, and the divider, and the controller forms a second loop with the second filter, the TDC, and the divider.
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公开(公告)号：US09893876B2
公开(公告)日：2018-02-13
申请号：US15156584
申请日：2016-05-17
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann
CPC classification number: H04L7/0331 , H03L7/091 , H03L7/093 , H03L7/0991 , H03L2207/50 , H04B1/12
Abstract: A phase locked loop, comprising: a phase detector configured to determine a phase difference (Δφ) between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.
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公开(公告)号：US20170194973A1
公开(公告)日：2017-07-06
申请号：US15377917
申请日：2016-12-13
Applicant: NXP B.V.
Inventor： Ulrich Moehlmann
CPC classification number: H03L7/0991 , G01S7/35 , H03L7/093 , H03L7/099 , H03L7/12 , H03L2207/06 , H03L2207/50
Abstract: An all digital phase locked loop system for tracking a variable frequency input signal and method of operation are described. The ADPLL system includes a digital phase locked loop, including a digitally controlled oscillator, and a model of the digitally controller oscillator. The model represents the behaviour of the digitally controlled oscillator as a function of frequency and has a model input arranged to receive a signal indicating a current target frequency. The model is configured to output at least one control signal to control the frequency of the digitally controlled oscillator to be closer to the current target frequency. The digital phase locked loop is configured to control the digitally controlled oscillator to reduce any difference between the frequency of the digitally controlled oscillator and the current target frequency arising from any deviation of the model of the digitally controlled oscillator from the digitally controlled oscillator.
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