Invention Grant
US09337850B2 All-digital phase-locked loop (ADPLL) with reduced settling time
有权
全数字锁相环（ADPLL），降低了建立时间
- Patent Title: All-digital phase-locked loop (ADPLL) with reduced settling time
- Patent Title (中): 全数字锁相环（ADPLL），降低了建立时间
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Application No.: US14446568Application Date: 2014-07-30
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Publication No.: US09337850B2Publication Date: 2016-05-10
- Inventor: Ulrich Moehlmann
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP, B.V.
- Current Assignee: NXP, B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/099
Abstract:
Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.
Public/Granted literature
- US20160036454A1 ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL) WITH REDUCED SETTLING TIME Public/Granted day:2016-02-04
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