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公开(公告)号：US20190199207A1
公开(公告)日：2019-06-27
申请号：US16137534
申请日：2018-09-20
Applicant: MEDIATEK INC.
Inventor： Yu-Li Hsueh , Chih-Hsien Shen , Chao-Ching Hung , Po-Chun Huang
Abstract: The present invention provides a charge pump including a pull-up circuit for selectively providing charges to an output terminal of the charge pump, and the pull-up circuit comprises a transistor, a capacitor and a switched-capacitor circuit, wherein the capacitor is coupled to an electrode of the transistor, and the switched-capacitor circuit is coupled between a supply voltage and another electrode of the transistor. The switched-capacitor circuit is configured to boost a voltage of the other electrode of the transistor to charge the capacitor via the transistor, then the capacitor and the output terminal of the charge pump are under a charge distribution operation.
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公开(公告)号：US11387813B2
公开(公告)日：2022-07-12
申请号：US17241044
申请日：2021-04-26
Applicant: MEDIATEK INC.
Inventor： Hsiu-Hsien Ting , Po-Chun Huang , Yu-Li Hsueh
Abstract: A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.
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Patent Agency Ranking
公开(公告)号：US20220123754A1
公开(公告)日：2022-04-21
申请号：US17462014
申请日：2021-08-31
Applicant: MEDIATEK INC.
Inventor： Po-Chun Huang , Yu-Li Hsueh
Abstract: A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.
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公开(公告)号：US20220069809A1
公开(公告)日：2022-03-03
申请号：US17241044
申请日：2021-04-26
Applicant: MEDIATEK INC.
Inventor： Hsiu-Hsien Ting , Po-Chun Huang , Yu-Li Hsueh
Abstract: A frequency multiplier and a delay-reused duty cycle calibration method thereof are provided. The frequency multiplier includes a first calibration circuit, a second calibration circuit and a controller. In a calibration mode of the frequency multiplier, an output terminal of a delay cell is coupled to an input terminal of the delay cell. The first calibration circuit repeatedly uses the delay cell M times for generating a first delayed signal. The controller controls the delay cell according to the first delayed signal, to find a delay of the delay cell which makes M times the delay be equal to one cycle period of an input clock signal. After the delay is found, the delay cell is repeatedly used M/2 times for generating a second delayed signal. The controller controls the second calibration circuit according to the second delayed signal to make an input calibration signal have a target duty cycle.
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公开(公告)号：US20220014227A1
公开(公告)日：2022-01-13
申请号：US17353351
申请日：2021-06-21
Applicant: MediaTek Inc.
Inventor： Yu-Hsien Chang , Po-Chun Huang , Pi-An Wu , Wen-Hsien Chiu , Tzu-Wen Sung
Abstract: Disclosed herein are devices and methods to reduce unwanted CIMS emission in a wireless communication device, such that the transmit (TX) power level applied in a RU can be increased without exceeding a regulatory emission requirement. In some aspects, unwanted emission may be reduced by shifting or changing local oscillator (LO) frequencies during TX operation. Some embodiments are directed to a fast-locking PLL with adjustable bandwidth that can be controlled to increase the PLL bandwidth during the RX to TX transition to provide a fast locking to a new LO frequency. Some aspects are directed to configuring an LO frequency shift amount for different RUs when multiple RUs are allocated within a frequency band.
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公开(公告)号：US20210091720A1
公开(公告)日：2021-03-25
申请号：US17026275
申请日：2020-09-20
Applicant: MEDIATEK INC.
Inventor： Chien-Wei Chen , Yu-Li Hsueh , Po-Chun Huang
Abstract: A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.
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公开(公告)号：US20200212843A1
公开(公告)日：2020-07-02
申请号：US16681771
申请日：2019-11-12
Applicant: MEDIATEK INC.
Inventor： Yu-Li Hsueh , Po-Chun Huang , Ang-Sheng Lin , Wei-Hao Chiu
IPC: H03B5/12
Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.
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